RE: [PATCH v2 3/4] dmaengine: sf-pdma: add mpfs-pdma compatible name

Shravan.Chippa
2023-10-04T03:48:02Z

Hi Emil Renner,

> -----Original Message-----
> From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Sent: Tuesday, October 3, 2023 1:05 PM
> To: shravan Chippa - I35088 <Shravan.Chippa@microchip.com>;
> green.wan@sifive.com; vkoul@kernel.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; palmer@dabbelt.com;
> paul.walmsley@sifive.com; conor+dt@kernel.org
> Cc: dmaengine@vger.kernel.org; devicetree@vger.kernel.org; linux-
> riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Nagasuresh Relli - I67208
> <Nagasuresh.Relli@microchip.com>; Praveen Kumar - I30718
> <Praveen.Kumar@microchip.com>
> Subject: Re: [PATCH v2 3/4] dmaengine: sf-pdma: add mpfs-pdma compatible
> name
>
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> shravan chippa wrote:
> > From: Shravan Chippa <shravan.chippa@microchip.com>
> >
> > Sifive platform dma does not allow out-of-order transfers, Add a
> > PolarFire SoC specific compatible and code to support for out-of-order
> > dma transfers
> >
> > Signed-off-by: Shravan Chippa <shravan.chippa@microchip.com>
> > ---
> > drivers/dma/sf-pdma/sf-pdma.c | 27 ++++++++++++++++++++++++---
> > drivers/dma/sf-pdma/sf-pdma.h | 6 ++++++
> > 2 files changed, 30 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/dma/sf-pdma/sf-pdma.c
> > b/drivers/dma/sf-pdma/sf-pdma.c index 06a0912a12a1..a9ff319d4ca3
> > 100644
> > --- a/drivers/dma/sf-pdma/sf-pdma.c
> > +++ b/drivers/dma/sf-pdma/sf-pdma.c
> > @@ -21,6 +21,7 @@
> > #include <linux/dma-mapping.h>
> > #include <linux/of.h>
> > #include <linux/of_dma.h>
> > +#include <linux/of_device.h>
> > #include <linux/slab.h>
> >
> > #include "sf-pdma.h"
> > @@ -66,7 +67,7 @@ static struct sf_pdma_desc
> > *sf_pdma_alloc_desc(struct sf_pdma_chan *chan) static void
> sf_pdma_fill_desc(struct sf_pdma_desc *desc,
> > u64 dst, u64 src, u64 size) {
> > - desc->xfer_type = PDMA_FULL_SPEED;
> > + desc->xfer_type = desc->chan->pdma->transfer_type;
>
> Two spaces.
>
> > desc->xfer_size = size;
> > desc->dst_addr = dst;
> > desc->src_addr = src;
> > @@ -520,6 +521,7 @@ static struct dma_chan *sf_pdma_of_xlate(struct
> of_phandle_args *dma_spec,
> >
> > static int sf_pdma_probe(struct platform_device *pdev)
> > {
> > + const struct sf_pdma_driver_platdata *ddata;
> > struct sf_pdma *pdma;
> > int ret, n_chans;
> > const enum dma_slave_buswidth widths =
> > @@ -545,6 +547,14 @@ static int sf_pdma_probe(struct platform_device
> *pdev)
> >
> > pdma->n_chans = n_chans;
> >
> > + pdma->transfer_type = PDMA_FULL_SPEED;
> > +
> > + ddata = of_device_get_match_data(&pdev->dev);
> > + if (ddata) {
> > + if (ddata->quirks & NO_STRICT_ORDERING)
> > + pdma->transfer_type &= ~(NO_STRICT_ORDERING);
> > + }
> > +
>
> The commit message says "Sifive platform dma does not allow out-of-order
> transfers" so you want strict ordering by default and then allow
> out-of-order transfers if the match data allows it, right?
>
> But here bit 3 is set by default and cleared if the quirk is set, so it looks
> like bit 3 actually means "strict ordering" and not "no strict ordering" as
> you've named it.
>
> The confusion here probably stems using the same define for the quirk and the
> xfer_type. Unless I'm mistaken above I'd find something like this a lot easier
> to read:
>
> sf_pdma.h:
> #define PDMA_FULL_SPEED 0xFF000000
> #define PDMA_STRICT_ORDERING BIT(3)
>
> sf_pdma.c:
> #define PDMA_QUIRK_NO_STRICT_ORDERING BIT(0)
>
> dma->transfer_type = PDMA_FULL_SPEED | PDMA_STRICT_ORDERING;
> ...
> if (ddata->quirks & PDMA_QUIRK_NO_STRICT_ORDERING)
> pdma->transfer_type &= ~PDMA_STRICT_ORDERING;
>

Thanks for the input. To avoid confusion on the naming of the macro and new macro for quirk
I will try to modify it as you mentioned.

Thanks,
Shravan

> > pdma->membase = devm_platform_ioremap_resource(pdev, 0);
> > if (IS_ERR(pdma->membase))
> > return PTR_ERR(pdma->membase);
> > @@ -632,11 +642,22 @@ static int sf_pdma_remove(struct platform_device
> *pdev)
> > return 0;
> > }
> >
> > +static const struct sf_pdma_driver_platdata mpfs_pdma = {
> > + .quirks = NO_STRICT_ORDERING,
> > +};
> > +
> > static const struct of_device_id sf_pdma_dt_ids[] = {
> > - { .compatible = "sifive,fu540-c000-pdma" },
> > - { .compatible = "sifive,pdma0" },
> > + {
> > + .compatible = "sifive,fu540-c000-pdma",
> > + }, {
> > + .compatible = "sifive,pdma0",
> > + }, {
> > + .compatible = "microchip,mpfs-pdma",
> > + .data = &mpfs_pdma,
> > + },
> > {},
> > };
> > +
> > MODULE_DEVICE_TABLE(of, sf_pdma_dt_ids);
> >
> > static struct platform_driver sf_pdma_driver = {
> > diff --git a/drivers/dma/sf-pdma/sf-pdma.h b/drivers/dma/sf-pdma/sf-pdma.h
> > index 5c398a83b491..3b16db4daa0b 100644
> > --- a/drivers/dma/sf-pdma/sf-pdma.h
> > +++ b/drivers/dma/sf-pdma/sf-pdma.h
> > @@ -49,6 +49,7 @@
> >
> > /* Transfer Type */
> > #define PDMA_FULL_SPEED 0xFF000008
> > +#define NO_STRICT_ORDERING BIT(3)
> >
> > /* Error Recovery */
> > #define MAX_RETRY 1
> > @@ -112,8 +113,13 @@ struct sf_pdma {
> > struct dma_device dma_dev;
> > void __iomem *membase;
> > void __iomem *mappedbase;
> > + u32 transfer_type;
> > u32 n_chans;
> > struct sf_pdma_chan chans[];
> > };
> >
> > +struct sf_pdma_driver_platdata {
> > + u32 quirks;
> > +};
> > +
> > #endif /* _SF_PDMA_H */
> > --
> > 2.34.1