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From: Andrew Jones <ajones@ventanamicro.com>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	linux-riscv@lists.infradead.org,
	 Paul Walmsley <paul.walmsley@sifive.com>,
	aou@eecs.berkeley.edu, Evan Green <evan@rivosinc.com>,
	 Conor Dooley <conor.dooley@microchip.com>,
	xiao.w.wang@intel.com
Subject: Re: [PATCH v4 2/6] RISC-V: Enable cbo.zero in usermode
Date: Tue, 10 Oct 2023 19:03:43 +0200	[thread overview]
Message-ID: <20231010-442c4eec837dbab30e4c65ae@orel> (raw)
In-Reply-To: <CAK9=C2WdpsHoWvour0vwnCmG01qZiGq4-BQSLa25QdZ-2DJF0g@mail.gmail.com>

On Thu, Sep 21, 2023 at 07:52:10PM +0530, Anup Patel wrote:
> On Thu, Sep 21, 2023 at 7:00 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
> >
> > On Mon, 18 Sep 2023 06:15:21 PDT (-0700), ajones@ventanamicro.com wrote:
...
> > > +void riscv_user_isa_enable(void)
> > > +{
> > > +     if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ))
> > > +             csr_set(CSR_SENVCFG, ENVCFG_CBZE);
> >
> > It looks like CBZE didn't actually get ratified?  The CMO extension says
> >
> >     _The CMO extensions rely on state in {csrname} CSRs that will be defined in a
> >     future update to the privileged architecture. If this CSR update is not
> >     ratified, the CMO extension will define its own CSRs._
> >
> > but the privileged spec says
> >
> >     The definition of the CBZE field will be furnished by the forthcoming
> >     Zicboz extension. Its allocation within `senvcfg` may change prior to
> >     the ratification of that extension.
> >
> > Is there some ratified spec that actually defines this?
> 
> I see what you mean. The integration of these bits into the RISC-V
> priv spec has not happened hence we have the non-normative text
> in the CMO specification. The bit positions in xenvcfg CSRs can't
> change because it's already part of ratified CMO specification and
> there are organizations (like Ventana) who have implemented these
> bits.
> 

Hi Palmer,

Does Anup's response satisfy the criteria for this? I'm wondering what, if
anything, I should do with this series. (The hwprobe-which-cpus series
is currently based on this series, because of the hwprobe selftests
changes, but I guess I could rework that.)

Thanks,
drew

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  reply	other threads:[~2023-10-10 17:04 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-18 13:15 [PATCH v4 0/6] RISC-V: Enable cbo.zero in usermode Andrew Jones
2023-09-18 13:15 ` [PATCH v4 1/6] RISC-V: Make zicbom/zicboz errors consistent Andrew Jones
2023-09-18 13:15 ` [PATCH v4 2/6] RISC-V: Enable cbo.zero in usermode Andrew Jones
2023-09-21 13:30   ` Palmer Dabbelt
2023-09-21 14:17     ` Anup Patel
2023-09-21 14:22     ` Anup Patel
2023-10-10 17:03       ` Andrew Jones [this message]
2023-09-18 13:15 ` [PATCH v4 3/6] RISC-V: hwprobe: Expose Zicboz extension and its block size Andrew Jones
2023-09-18 13:15 ` [PATCH v4 4/6] RISC-V: selftests: Statically link hwprobe test Andrew Jones
2023-09-18 13:15 ` [PATCH v4 5/6] RISC-V: selftests: Convert hwprobe test to kselftest API Andrew Jones
2023-09-18 13:15 ` [PATCH v4 6/6] RISC-V: selftests: Add CBO tests Andrew Jones
2023-09-20  5:41   ` Wang, Xiao W

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