From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Cc: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
"Rob Herring" <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Philipp Zabel <p.zabel@pengutronix.de>,
Walker Chen <walker.chen@starfivetech.com>,
Xingyu Wu <xingyu.wu@starfivetech.com>,
"Samin Guo" <samin.guo@starfivetech.com>,
<linux-kernel@vger.kernel.org>, "Conor Dooley" <conor@kernel.org>
Subject: [PATCH v7 3/3] riscv: dts: jh7110: starfive: Add timer node
Date: Thu, 19 Oct 2023 13:35:01 +0800 [thread overview]
Message-ID: <20231019053501.46899-4-xingyu.wu@starfivetech.com> (raw)
In-Reply-To: <20231019053501.46899-1-xingyu.wu@starfivetech.com>
Add the timer node for the Starfive JH7110 SoC.
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index e85464c328d0..76062130d26e 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -811,6 +811,26 @@ sysgpio: pinctrl@13040000 {
#gpio-cells = <2>;
};
+ timer@13050000 {
+ compatible = "starfive,jh7110-timer";
+ reg = <0x0 0x13050000 0x0 0x10000>;
+ interrupts = <69>, <70>, <71>, <72>;
+ clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>,
+ <&syscrg JH7110_SYSCLK_TIMER0>,
+ <&syscrg JH7110_SYSCLK_TIMER1>,
+ <&syscrg JH7110_SYSCLK_TIMER2>,
+ <&syscrg JH7110_SYSCLK_TIMER3>;
+ clock-names = "apb", "ch0", "ch1",
+ "ch2", "ch3";
+ resets = <&syscrg JH7110_SYSRST_TIMER_APB>,
+ <&syscrg JH7110_SYSRST_TIMER0>,
+ <&syscrg JH7110_SYSRST_TIMER1>,
+ <&syscrg JH7110_SYSRST_TIMER2>,
+ <&syscrg JH7110_SYSRST_TIMER3>;
+ reset-names = "apb", "ch0", "ch1",
+ "ch2", "ch3";
+ };
+
watchdog@13070000 {
compatible = "starfive,jh7110-wdt";
reg = <0x0 0x13070000 0x0 0x10000>;
--
2.25.1
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prev parent reply other threads:[~2023-10-19 5:36 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-19 5:34 [PATCH v7 0/3] Add timer driver for StarFive JH7110 RISC-V SoC Xingyu Wu
2023-10-19 5:34 ` [PATCH v7 1/3] dt-bindings: timer: Add timer for StarFive JH7110 SoC Xingyu Wu
2023-10-19 5:35 ` [PATCH v7 2/3] clocksource: Add JH7110 timer driver Xingyu Wu
2023-10-24 13:13 ` Emil Renner Berthing
2023-10-25 8:39 ` Xingyu Wu
2023-10-24 14:56 ` Daniel Lezcano
2023-10-25 9:04 ` Xingyu Wu
2023-10-25 14:39 ` Daniel Lezcano
2023-10-27 9:17 ` Xingyu Wu
[not found] ` <65c38717-3e0c-46d3-a124-29cae48f1a2e@linaro.org>
2023-11-02 13:15 ` Xingyu Wu
2023-11-02 14:29 ` Daniel Lezcano
2023-11-08 3:45 ` Xingyu Wu
2023-11-08 9:10 ` Daniel Lezcano
2023-11-09 7:51 ` Xingyu Wu
2023-11-10 17:40 ` Samuel Holland
2023-11-10 18:02 ` Daniel Lezcano
2023-11-13 2:19 ` Xingyu Wu
2023-10-19 5:35 ` Xingyu Wu [this message]
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