From: Yu Chien Peter Lin <peterlin@andestech.com>
To: <geert+renesas@glider.be>, <magnus.damm@gmail.com>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<conor+dt@kernel.org>, <paul.walmsley@sifive.com>,
<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
<linux-renesas-soc@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Cc: <prabhakar.mahadev-lad.rj@bp.renesas.com>, <tim609@andestech.com>,
<dylan@andestech.com>, <locus84@andestech.com>,
<dminus@andestech.com>,
"Yu Chien Peter Lin" <peterlin@andestech.com>
Subject: [PATCH v2 09/10] riscv: dts: renesas: Add Andes PMU extension
Date: Thu, 19 Oct 2023 22:02:32 +0800 [thread overview]
Message-ID: <20231019140232.3660375-1-peterlin@andestech.com> (raw)
Add "xandespmu" to ISA extensions, the SBI PMU driver will
probe the extension and use the non-standard irq source.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v1 -> v2:
- New patch
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index a6345469e8c9..73c572056a04 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -26,7 +26,7 @@ cpu0: cpu@0 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
- "zifencei", "zihpm";
+ "zifencei", "zihpm", "xandespmu";
mmu-type = "riscv,sv39";
i-cache-size = <0x8000>;
i-cache-line-size = <0x40>;
--
2.34.1
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next reply other threads:[~2023-10-19 14:06 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-19 14:02 Yu Chien Peter Lin [this message]
2023-10-20 7:32 ` [PATCH v2 09/10] riscv: dts: renesas: Add Andes PMU extension Geert Uytterhoeven
2023-10-20 8:20 ` Yu-Chien Peter Lin
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