From: Charlie Jenkins <charlie@rivosinc.com>
To: Charlie Jenkins <charlie@rivosinc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Conor Dooley <conor@kernel.org>,
Samuel Holland <samuel.holland@sifive.com>,
David Laight <David.Laight@aculab.com>,
Xiao Wang <xiao.w.wang@intel.com>,
Evan Green <evan@rivosinc.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-arch@vger.kernel.org
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>, Arnd Bergmann <arnd@arndb.de>
Subject: [PATCH v8 2/5] riscv: Add static key for misaligned accesses
Date: Fri, 27 Oct 2023 15:43:52 -0700 [thread overview]
Message-ID: <20231027-optimize_checksum-v8-2-feb7101d128d@rivosinc.com> (raw)
In-Reply-To: <20231027-optimize_checksum-v8-0-feb7101d128d@rivosinc.com>
Support static branches depending on the value of misaligned accesses.
This will be used by a later patch in the series. All cpus must be
considered "fast" for this static branch to be flipped.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
arch/riscv/include/asm/cpufeature.h | 3 +++
arch/riscv/kernel/cpufeature.c | 30 ++++++++++++++++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
index b139796392d0..febd9de4373e 100644
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -7,6 +7,7 @@
#define _ASM_CPUFEATURE_H
#include <linux/bitmap.h>
+#include <linux/jump_label.h>
#include <asm/hwcap.h>
/*
@@ -32,4 +33,6 @@ extern struct riscv_isainfo hart_isa[NR_CPUS];
int check_unaligned_access(void *unused);
+DECLARE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key);
+
#endif
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 40bb854fcb96..8935481d32da 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -9,6 +9,7 @@
#include <linux/acpi.h>
#include <linux/bitmap.h>
#include <linux/ctype.h>
+#include <linux/jump_label.h>
#include <linux/log2.h>
#include <linux/memory.h>
#include <linux/module.h>
@@ -665,6 +666,35 @@ static int check_unaligned_access_all_cpus(void)
arch_initcall(check_unaligned_access_all_cpus);
+DEFINE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key);
+
+static int set_unaligned_access_static_branches(void)
+{
+ /*
+ * This will be called after check_unaligned_access_all_cpus so the
+ * result of unaligned access speed for all cpus will be available.
+ */
+
+ int cpu;
+ bool fast_misaligned_access_speed = true;
+
+ for_each_online_cpu(cpu) {
+ int this_perf = per_cpu(misaligned_access_speed, cpu);
+
+ if (this_perf != RISCV_HWPROBE_MISALIGNED_FAST) {
+ fast_misaligned_access_speed = false;
+ break;
+ }
+ }
+
+ if (fast_misaligned_access_speed)
+ static_branch_enable(&fast_misaligned_access_speed_key);
+
+ return 0;
+}
+
+arch_initcall_sync(set_unaligned_access_static_branches);
+
#ifdef CONFIG_RISCV_ALTERNATIVE
/*
* Alternative patch sites consider 48 bits when determining when to patch
--
2.42.0
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next prev parent reply other threads:[~2023-10-27 22:44 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-27 22:43 [PATCH v8 0/5] riscv: Add fine-tuned checksum functions Charlie Jenkins
2023-10-27 22:43 ` [PATCH v8 1/5] asm-generic: Improve csum_fold Charlie Jenkins
2023-10-27 23:10 ` Al Viro
2023-10-28 0:04 ` Charlie Jenkins
2023-10-27 22:43 ` Charlie Jenkins [this message]
2023-10-27 22:43 ` [PATCH v8 3/5] riscv: Checksum header Charlie Jenkins
2023-10-31 9:11 ` Wang, Xiao W
2023-10-31 22:53 ` Charlie Jenkins
2023-10-27 22:43 ` [PATCH v8 4/5] riscv: Add checksum library Charlie Jenkins
2023-10-31 9:51 ` Wang, Xiao W
2023-10-31 22:59 ` Charlie Jenkins
2023-10-27 22:43 ` [PATCH v8 5/5] riscv: Test checksum functions Charlie Jenkins
2023-10-31 7:57 ` [PATCH v8 0/5] riscv: Add fine-tuned " Conor Dooley
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