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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id x16-20020a4a97d0000000b0057327cecdd8sm2535510ooi.10.2023.11.08.09.12.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Nov 2023 09:12:04 -0800 (PST) Received: (nullmailer pid 2492952 invoked by uid 1000); Wed, 08 Nov 2023 17:12:03 -0000 Date: Wed, 8 Nov 2023 11:12:03 -0600 From: Rob Herring To: Michal Simek Cc: linux-kernel@vger.kernel.org, monstr@monstr.eu, michal.simek@xilinx.com, git@xilinx.com, Albert Ou , Conor Dooley , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH] dt-bindings: riscv: cpus: Add AMD MicroBlaze V compatible Message-ID: <20231108171203.GA2434548-robh@kernel.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231108_091205_691020_444345E7 X-CRM114-Status: GOOD ( 13.86 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Nov 06, 2023 at 12:37:47PM +0100, Michal Simek wrote: > MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. > It is hardware compatible with classic MicroBlaze processor. How is that possible? It's a different instruction set, right? I suppose the IP interfaces (signals) are the same/compatible. > > Signed-off-by: Michal Simek > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) Anyways, Acked-by: Rob Herring > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 97e8441eda1c..7b077af62b27 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -32,6 +32,7 @@ properties: > oneOf: > - items: > - enum: > + - amd,mbv32 > - andestech,ax45mp > - canaan,k210 > - sifive,bullet0 > -- > 2.36.1 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv