From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C5369C61D97 for ; Fri, 24 Nov 2023 11:54:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=kdgKFaUGnoH021YshOkzamfMQFYuE8RQIaD+4lXH3ag=; b=gl0RKTZakdqJTB Rx+3I5WmdXESR3in49TeMY8XXz3byfIDF4uwXd0tZevsqHEWYdDCdM4z2/UVbbf7B+htLNXjskVOF YDurYxRsJQJfQE2W5Y6Cyrgcmp71BZRiUdn6nbwJ6yM7Rba2nFzde5OqHkTvTawOMUEXOQB1GA8Ic UWZuq/VbN3Z0oxOTJQOCzpAB/czS1TYufsM48DPTEDlX1Fly6hg/lR/ZwT45srMWvKte4yVeABEdw jK1fWxkyY6D/D5Ai+uaIVIIwX4PRGUodf7LTkW6E4oBC0tP7yJEFuG4YrM4Iu/KF39j40HMyQAdb3 Igl1rmzEGMImUOZGGDnw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r6Ulh-00757j-0M; Fri, 24 Nov 2023 11:54:45 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r6Ulf-00755x-0e for linux-riscv@bombadil.infradead.org; Fri, 24 Nov 2023 11:54:43 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=7/9ELPCZSyNtTedfYVN0RIERqDSGzyj/VTh+0OOKOJ4=; b=Gqm+SH2WxYC3SW6jehiqHEIGvx onKuc1sq6cP7JYqCQV6I+k3G+jf98LkqC9B3LwKbgLMdVmBHLwLlEv/AGXM2juldAAUNh+/+Ifia3 fjZe0lqpVvdtm+F+QoWzePxPpF+WHQnoTB305XXBJyQLbB9dNgFiunMC7PtaqJynhX7bXUDVkgybK tp029/O+KPQ1PiTV/JUSbhwK1ia7A/XvEG/q632FVmhOyfHIxoYpyiGh/MB2MIEGw6+6eWQwVBJNa E5CYY1M/QHrPtjv7Cu6Upz2QHzs/SFLveqZO6rIX148LBb/akZPQ+ZK7VhyuNsfhS6tn6s4CJEN27 WO4O9WCQ==; Received: from j130084.upc-j.chello.nl ([24.132.130.84] helo=noisy.programming.kicks-ass.net) by desiato.infradead.org with esmtpsa (Exim 4.96 #2 (Red Hat Linux)) id 1r6UlU-00DsrU-3A; Fri, 24 Nov 2023 11:54:34 +0000 Received: by noisy.programming.kicks-ass.net (Postfix, from userid 1000) id 86BF03002BE; Fri, 24 Nov 2023 12:54:30 +0100 (CET) Date: Fri, 24 Nov 2023 12:54:30 +0100 From: Peter Zijlstra To: Jonas Oberhauser Cc: Christoph Muellner , linux-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Albert Ou , Andrew Morton , Shuah Khan , Jonathan Corbet , Anup Patel , Philipp Tomsich , Andrew Jones , Guo Ren , Daniel Henrique Barboza , Conor Dooley , =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= , Alan Stern , Andrea Parri , Will Deacon , Daniel Lustig Subject: Re: [RFC PATCH 0/5] RISC-V: Add dynamic TSO support Message-ID: <20231124115430.GS3818@noisy.programming.kicks-ass.net> References: <20231124072142.2786653-1-christoph.muellner@vrull.eu> <20231124101519.GP3818@noisy.programming.kicks-ass.net> <59da3e41-abb3-405a-8f98-c74bdf26935b@huaweicloud.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <59da3e41-abb3-405a-8f98-c74bdf26935b@huaweicloud.com> X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Nov 24, 2023 at 12:04:09PM +0100, Jonas Oberhauser wrote: > > I think ARM64 approached this problem by adding the > > load-acquire/store-release instructions and for TSO based code, > > translate into those (eg. x86 -> arm64 transpilers). > > > Although those instructions have a bit more ordering constraints. > > I have heard rumors that the apple chips also have a register that can be > set at runtime. Oh, I thought they made do with the load-acquire/store-release thingies. But to be fair, I haven't been paying *that* much attention to the apple stuff. I did read about how they fudged some of the x86 flags thing. > And there are some IBM machines that have a setting, but not sure how it is > controlled. Cute, I'm assuming this is the Power series (s390 already being TSO)? I wasn't aware they had this. > > IIRC Risc-V actually has such instructions as well, so *why* are you > > doing this?!?! > > > Unfortunately, at least last time I checked RISC-V still hadn't gotten such > instructions. > What they have is the *semantics* of the instructions, but no actual opcodes > to encode them. Well, that sucks.. > I argued for them in the RISC-V memory group, but it was considered to be > outside the scope of that group. > > Transpiling with sufficient DMB ISH to get the desired ordering is really > bad for performance. Ha!, quite dreadful I would imagine. > That is not to say that linux should support this. Perhaps linux should > pressure RISC-V into supporting implicit barriers instead. I'm not sure I count for much in this regard, but yeah, that sounds like a plan :-) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv