From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
kvm@vger.kernel.org
Cc: anup@brainfault.org, atishp@atishpatra.org, palmer@dabbelt.com,
ajones@ventanamicro.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH 2/3] RISC-V: KVM: add 'vlenb' Vector CSR
Date: Mon, 4 Dec 2023 15:29:03 -0300 [thread overview]
Message-ID: <20231204182905.2163676-3-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20231204182905.2163676-1-dbarboza@ventanamicro.com>
Userspace requires 'vlenb' to be able to encode it in reg ID. Otherwise
it is not possible to retrieve any vector reg since we're returning
EINVAL if reg_size isn't vlenb (see kvm_riscv_vcpu_vreg_addr()).
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
arch/riscv/kvm/vcpu_vector.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/riscv/kvm/vcpu_vector.c b/arch/riscv/kvm/vcpu_vector.c
index 530e49c588d6..d92d1348045c 100644
--- a/arch/riscv/kvm/vcpu_vector.c
+++ b/arch/riscv/kvm/vcpu_vector.c
@@ -116,6 +116,9 @@ static int kvm_riscv_vcpu_vreg_addr(struct kvm_vcpu *vcpu,
case KVM_REG_RISCV_VECTOR_CSR_REG(vcsr):
*reg_addr = &cntx->vector.vcsr;
break;
+ case KVM_REG_RISCV_VECTOR_CSR_REG(vlenb):
+ *reg_addr = &cntx->vector.vlenb;
+ break;
case KVM_REG_RISCV_VECTOR_CSR_REG(datap):
default:
return -ENOENT;
@@ -174,6 +177,18 @@ int kvm_riscv_vcpu_set_reg_vector(struct kvm_vcpu *vcpu,
if (!riscv_isa_extension_available(isa, v))
return -ENOENT;
+ if (reg_num == KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)) {
+ struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
+ unsigned long reg_val;
+
+ if (copy_from_user(®_val, uaddr, reg_size))
+ return -EFAULT;
+ if (reg_val != cntx->vector.vlenb)
+ return -EINVAL;
+
+ return 0;
+ }
+
rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, ®_addr);
if (rc)
return rc;
--
2.41.0
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next prev parent reply other threads:[~2023-12-04 18:29 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-04 18:29 [PATCH 0/3] RISC-V, KVM: add 'vlenb' and vector CSRs to get-reg-list Daniel Henrique Barboza
2023-12-04 18:29 ` [PATCH 1/3] RISC-V: KVM: set 'vlenb' in kvm_riscv_vcpu_alloc_vector_context() Daniel Henrique Barboza
2023-12-04 18:29 ` Daniel Henrique Barboza [this message]
2023-12-04 18:29 ` [PATCH 3/3] RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST Daniel Henrique Barboza
2023-12-05 13:22 ` kernel test robot
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