[PATCH 0/3] RISC-V, KVM: add 'vlenb' and vector CSRs to get-reg-list

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* [PATCH 0/3] RISC-V, KVM: add 'vlenb' and vector CSRs to get-reg-list
@ 2023-12-04 18:29 Daniel Henrique Barboza
  2023-12-04 18:29 ` [PATCH 1/3] RISC-V: KVM: set 'vlenb' in kvm_riscv_vcpu_alloc_vector_context() Daniel Henrique Barboza
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Daniel Henrique Barboza @ 2023-12-04 18:29 UTC (permalink / raw)
  To: kvm-riscv, linux-riscv, kvm
  Cc: anup, atishp, palmer, ajones, Daniel Henrique Barboza

Hi,

At this moment we have the following problems in our Vector KVM support:

- we need a way to deliver 'vlenb' to userspace. Otherwise it's not
  possible to determine the right vector regs IDs (since they vary with
  vlenb). In fact, KVM will error out if 'vlenb' has the wrong size,
  even for vector reg 0;

- an appropriate way of delivering 'vlenb' is via get-reg-list, which
  ATM doesn't have any vector CSRs;

- even if we do all that, we're not initializing 'vlenb' at any point.
  Userspace will read vlenb = 0 and won't be able to do much with it.


This series aims to attempts to fix all these problems.


Daniel Henrique Barboza (3):
  RISC-V: KVM: set 'vlenb' in kvm_riscv_vcpu_alloc_vector_context()
  RISC-V: KVM: add 'vlenb' Vector CSR
  RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST

 arch/riscv/kvm/vcpu_onereg.c | 37 ++++++++++++++++++++++++++++++++++++
 arch/riscv/kvm/vcpu_vector.c | 16 ++++++++++++++++
 2 files changed, 53 insertions(+)

-- 
2.41.0


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^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 1/3] RISC-V: KVM: set 'vlenb' in kvm_riscv_vcpu_alloc_vector_context()
  2023-12-04 18:29 [PATCH 0/3] RISC-V, KVM: add 'vlenb' and vector CSRs to get-reg-list Daniel Henrique Barboza
@ 2023-12-04 18:29 ` Daniel Henrique Barboza
  2023-12-04 18:29 ` [PATCH 2/3] RISC-V: KVM: add 'vlenb' Vector CSR Daniel Henrique Barboza
  2023-12-04 18:29 ` [PATCH 3/3] RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST Daniel Henrique Barboza
  2 siblings, 0 replies; 5+ messages in thread
From: Daniel Henrique Barboza @ 2023-12-04 18:29 UTC (permalink / raw)
  To: kvm-riscv, linux-riscv, kvm
  Cc: anup, atishp, palmer, ajones, Daniel Henrique Barboza

'vlenb', added to riscv_v_ext_state by commit c35f3aa34509 ("RISC-V:
vector: export VLENB csr in __sc_riscv_v_state"), isn't being
initialized in guest_context. If we export 'vlenb' as a KVM CSR,
something we want to do in the next patch, it'll always return 0.

Set 'vlenb' to riscv_v_size/32.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 arch/riscv/kvm/vcpu_vector.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/kvm/vcpu_vector.c b/arch/riscv/kvm/vcpu_vector.c
index b339a2682f25..530e49c588d6 100644
--- a/arch/riscv/kvm/vcpu_vector.c
+++ b/arch/riscv/kvm/vcpu_vector.c
@@ -76,6 +76,7 @@ int kvm_riscv_vcpu_alloc_vector_context(struct kvm_vcpu *vcpu,
 	cntx->vector.datap = kmalloc(riscv_v_vsize, GFP_KERNEL);
 	if (!cntx->vector.datap)
 		return -ENOMEM;
+	cntx->vector.vlenb = riscv_v_vsize / 32;
 
 	vcpu->arch.host_context.vector.datap = kzalloc(riscv_v_vsize, GFP_KERNEL);
 	if (!vcpu->arch.host_context.vector.datap)
-- 
2.41.0


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^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [PATCH 2/3] RISC-V: KVM: add 'vlenb' Vector CSR
  2023-12-04 18:29 [PATCH 0/3] RISC-V, KVM: add 'vlenb' and vector CSRs to get-reg-list Daniel Henrique Barboza
  2023-12-04 18:29 ` [PATCH 1/3] RISC-V: KVM: set 'vlenb' in kvm_riscv_vcpu_alloc_vector_context() Daniel Henrique Barboza
@ 2023-12-04 18:29 ` Daniel Henrique Barboza
  2023-12-04 18:29 ` [PATCH 3/3] RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST Daniel Henrique Barboza
  2 siblings, 0 replies; 5+ messages in thread
From: Daniel Henrique Barboza @ 2023-12-04 18:29 UTC (permalink / raw)
  To: kvm-riscv, linux-riscv, kvm
  Cc: anup, atishp, palmer, ajones, Daniel Henrique Barboza

Userspace requires 'vlenb' to be able to encode it in reg ID. Otherwise
it is not possible to retrieve any vector reg since we're returning
EINVAL if reg_size isn't vlenb (see kvm_riscv_vcpu_vreg_addr()).

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 arch/riscv/kvm/vcpu_vector.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/riscv/kvm/vcpu_vector.c b/arch/riscv/kvm/vcpu_vector.c
index 530e49c588d6..d92d1348045c 100644
--- a/arch/riscv/kvm/vcpu_vector.c
+++ b/arch/riscv/kvm/vcpu_vector.c
@@ -116,6 +116,9 @@ static int kvm_riscv_vcpu_vreg_addr(struct kvm_vcpu *vcpu,
 		case KVM_REG_RISCV_VECTOR_CSR_REG(vcsr):
 			*reg_addr = &cntx->vector.vcsr;
 			break;
+		case KVM_REG_RISCV_VECTOR_CSR_REG(vlenb):
+			*reg_addr = &cntx->vector.vlenb;
+			break;
 		case KVM_REG_RISCV_VECTOR_CSR_REG(datap):
 		default:
 			return -ENOENT;
@@ -174,6 +177,18 @@ int kvm_riscv_vcpu_set_reg_vector(struct kvm_vcpu *vcpu,
 	if (!riscv_isa_extension_available(isa, v))
 		return -ENOENT;
 
+	if (reg_num == KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)) {
+		struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
+		unsigned long reg_val;
+
+		if (copy_from_user(&reg_val, uaddr, reg_size))
+			return -EFAULT;
+		if (reg_val != cntx->vector.vlenb)
+			return -EINVAL;
+
+		return 0;
+	}
+
 	rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, &reg_addr);
 	if (rc)
 		return rc;
-- 
2.41.0


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^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [PATCH 3/3] RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST
  2023-12-04 18:29 [PATCH 0/3] RISC-V, KVM: add 'vlenb' and vector CSRs to get-reg-list Daniel Henrique Barboza
  2023-12-04 18:29 ` [PATCH 1/3] RISC-V: KVM: set 'vlenb' in kvm_riscv_vcpu_alloc_vector_context() Daniel Henrique Barboza
  2023-12-04 18:29 ` [PATCH 2/3] RISC-V: KVM: add 'vlenb' Vector CSR Daniel Henrique Barboza
@ 2023-12-04 18:29 ` Daniel Henrique Barboza
  2023-12-05 13:22   ` kernel test robot
  2 siblings, 1 reply; 5+ messages in thread
From: Daniel Henrique Barboza @ 2023-12-04 18:29 UTC (permalink / raw)
  To: kvm-riscv, linux-riscv, kvm
  Cc: anup, atishp, palmer, ajones, Daniel Henrique Barboza

Add all vector CSRs (vstart, vl, vtype, vcsr, vlenb) in get-reg-list.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 arch/riscv/kvm/vcpu_onereg.c | 37 ++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index f8c9fa0c03c5..1c91615f47cc 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -986,6 +986,37 @@ static int copy_sbi_ext_reg_indices(u64 __user *uindices)
 	return num_sbi_ext_regs();
 }
 
+static inline unsigned long num_vector_regs(const struct kvm_vcpu *vcpu)
+{
+	const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
+
+	if (!riscv_isa_extension_available(vcpu->arch.isa, v))
+		return 0;
+
+	/* vstart, vl, vtype, vcsr, vlenb; */
+	return 5;
+}
+
+static int copy_vector_reg_indices(const struct kvm_vcpu *vcpu,
+				u64 __user *uindices)
+{
+	int n = num_vector_regs(vcpu);
+	u64 reg, size;
+
+	for (int i = 0; i < n; i++) {
+		size = IS_ENABLED(CONFIG_32BIT) ? KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64;
+		reg = KVM_REG_RISCV | size | KVM_REG_RISCV_VECTOR | i;
+
+		if (uindices) {
+			if (put_user(reg, uindices))
+				return -EFAULT;
+			uindices++;
+		}
+	}
+
+	return n;
+}
+
 /*
  * kvm_riscv_vcpu_num_regs - how many registers do we present via KVM_GET/SET_ONE_REG
  *
@@ -1001,6 +1032,7 @@ unsigned long kvm_riscv_vcpu_num_regs(struct kvm_vcpu *vcpu)
 	res += num_timer_regs();
 	res += num_fp_f_regs(vcpu);
 	res += num_fp_d_regs(vcpu);
+	res += num_vector_regs(vcpu);
 	res += num_isa_ext_regs(vcpu);
 	res += num_sbi_ext_regs();
 
@@ -1045,6 +1077,11 @@ int kvm_riscv_vcpu_copy_reg_indices(struct kvm_vcpu *vcpu,
 		return ret;
 	uindices += ret;
 
+	ret = copy_vector_reg_indices(vcpu, uindices);
+	if (ret < 0)
+		return ret;
+	uindices += ret;
+
 	ret = copy_isa_ext_reg_indices(vcpu, uindices);
 	if (ret < 0)
 		return ret;
-- 
2.41.0


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^ permalink raw reply related	[flat|nested] 5+ messages in thread

* Re: [PATCH 3/3] RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST
  2023-12-04 18:29 ` [PATCH 3/3] RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST Daniel Henrique Barboza
@ 2023-12-05 13:22   ` kernel test robot
  0 siblings, 0 replies; 5+ messages in thread
From: kernel test robot @ 2023-12-05 13:22 UTC (permalink / raw)
  To: Daniel Henrique Barboza, kvm-riscv, linux-riscv, kvm
  Cc: oe-kbuild-all, anup, atishp, palmer, ajones,
	Daniel Henrique Barboza

Hi Daniel,

kernel test robot noticed the following build warnings:

[auto build test WARNING on kvm/queue]
[also build test WARNING on mst-vhost/linux-next linus/master v6.7-rc4 next-20231205]
[cannot apply to kvm/linux-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Daniel-Henrique-Barboza/RISC-V-KVM-set-vlenb-in-kvm_riscv_vcpu_alloc_vector_context/20231205-023109
base:   https://git.kernel.org/pub/scm/virt/kvm/kvm.git queue
patch link:    https://lore.kernel.org/r/20231204182905.2163676-4-dbarboza%40ventanamicro.com
patch subject: [PATCH 3/3] RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST
config: riscv-defconfig (https://download.01.org/0day-ci/archive/20231205/202312052128.oBSS3Uus-lkp@intel.com/config)
compiler: riscv64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231205/202312052128.oBSS3Uus-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202312052128.oBSS3Uus-lkp@intel.com/

All warnings (new ones prefixed by >>):

   arch/riscv/kvm/vcpu_onereg.c: In function 'num_vector_regs':
>> arch/riscv/kvm/vcpu_onereg.c:991:39: warning: unused variable 'cntx' [-Wunused-variable]
     991 |         const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
         |                                       ^~~~


vim +/cntx +991 arch/riscv/kvm/vcpu_onereg.c

   988	
   989	static inline unsigned long num_vector_regs(const struct kvm_vcpu *vcpu)
   990	{
 > 991		const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
   992	
   993		if (!riscv_isa_extension_available(vcpu->arch.isa, v))
   994			return 0;
   995	
   996		/* vstart, vl, vtype, vcsr, vlenb; */
   997		return 5;
   998	}
   999	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

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Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2023-12-04 18:29 [PATCH 0/3] RISC-V, KVM: add 'vlenb' and vector CSRs to get-reg-list Daniel Henrique Barboza
2023-12-04 18:29 ` [PATCH 1/3] RISC-V: KVM: set 'vlenb' in kvm_riscv_vcpu_alloc_vector_context() Daniel Henrique Barboza
2023-12-04 18:29 ` [PATCH 2/3] RISC-V: KVM: add 'vlenb' Vector CSR Daniel Henrique Barboza
2023-12-04 18:29 ` [PATCH 3/3] RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST Daniel Henrique Barboza
2023-12-05 13:22   ` kernel test robot

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