From: Conor Dooley <conor@kernel.org>
To: linux-riscv@lists.infradead.org
Cc: conor@kernel.org, Conor Dooley <conor.dooley@microchip.com>,
Daire McNamara <daire.mcnamara@microchip.com>,
Wolfgang Grandegger <wg@grandegger.com>,
Marc Kleine-Budde <mkl@pengutronix.de>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-can@vger.kernel.org, netdev@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org
Subject: [PATCH RESEND v1 7/7] riscv: dts: microchip: add missing CAN bus clocks
Date: Fri, 8 Dec 2023 17:12:29 +0000 [thread overview]
Message-ID: <20231208-resample-selection-3c2c8cecc489@spud> (raw)
In-Reply-To: <20231208-reenter-ajar-b6223e5134b3@spud>
From: Conor Dooley <conor.dooley@microchip.com>
The CAN controller on PolarFire SoC has an AHB peripheral clock _and_ a
CAN bus clock. The bus clock was omitted when the binding was written,
but is required for operation. Make up for lost time and add to the DT.
Fixes: 38a71fc04895 ("riscv: dts: microchip: add mpfs's CAN controllers")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/microchip/mpfs.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 266489d43912..4d70df0f908c 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -416,7 +416,7 @@ i2c1: i2c@2010b000 {
can0: can@2010c000 {
compatible = "microchip,mpfs-can";
reg = <0x0 0x2010c000 0x0 0x1000>;
- clocks = <&clkcfg CLK_CAN0>;
+ clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>;
interrupt-parent = <&plic>;
interrupts = <56>;
status = "disabled";
@@ -425,7 +425,7 @@ can0: can@2010c000 {
can1: can@2010d000 {
compatible = "microchip,mpfs-can";
reg = <0x0 0x2010d000 0x0 0x1000>;
- clocks = <&clkcfg CLK_CAN1>;
+ clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>;
interrupt-parent = <&plic>;
interrupts = <57>;
status = "disabled";
--
2.39.2
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next prev parent reply other threads:[~2023-12-08 17:13 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-08 17:12 [PATCH RESEND v1 0/7] MPFS clock fixes required for correct CAN clock modeling Conor Dooley
2023-12-08 17:12 ` [PATCH RESEND v1 1/7] dt-bindings: clock: mpfs: add more MSSPLL output definitions Conor Dooley
2023-12-08 17:40 ` Emil Renner Berthing
2023-12-08 19:26 ` Conor Dooley
2023-12-09 7:58 ` Krzysztof Kozlowski
2023-12-08 17:12 ` [PATCH RESEND v1 2/7] dt-bindings: can: mpfs: add missing required clock Conor Dooley
2023-12-08 18:31 ` Rob Herring
2023-12-08 19:25 ` Conor Dooley
2023-12-08 21:42 ` Rob Herring
2023-12-12 20:49 ` Marc Kleine-Budde
2023-12-13 13:02 ` Conor Dooley
2023-12-14 11:31 ` Marc Kleine-Budde
2023-12-14 13:16 ` Conor Dooley
2023-12-14 13:20 ` Marc Kleine-Budde
2023-12-08 17:12 ` [PATCH RESEND v1 3/7] clk: microchip: mpfs: split MSSPLL in two Conor Dooley
2023-12-08 17:12 ` [PATCH RESEND v1 4/7] clk: microchip: mpfs: setup for using other mss pll outputs Conor Dooley
2023-12-08 17:12 ` [PATCH RESEND v1 5/7] clk: microchip: mpfs: add missing MSSPLL outputs Conor Dooley
2023-12-08 17:12 ` [PATCH RESEND v1 6/7] clk: microchip: mpfs: convert MSSPLL outputs to clk_divider Conor Dooley
2023-12-08 17:12 ` Conor Dooley [this message]
2023-12-08 17:17 ` [PATCH RESEND v1 0/7] MPFS clock fixes required for correct CAN clock modeling Marc Kleine-Budde
2023-12-08 17:21 ` Conor Dooley
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