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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id fm14-20020a05600c0c0e00b00407b93d8085sm22968185wmb.27.2023.12.13.06.02.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 06:02:52 -0800 (PST) Date: Wed, 13 Dec 2023 15:02:51 +0100 From: Andrew Jones To: Haibo Xu Cc: xiaobo55x@gmail.com, Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Shuah Khan , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Anup Patel , Atish Patra , Guo Ren , Conor Dooley , Mayuresh Chitale , Daniel Henrique Barboza , Jisheng Zhang , Samuel Holland , Minda Chen , Sean Christopherson , Peter Xu , Like Xu , Vipin Sharma , Maciej Wieczor-Retman , Thomas Huth , Aaron Lewis , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm-riscv@lists.infradead.org Subject: Re: [PATCH v4 05/11] tools: riscv: Add header file vdso/processor.h Message-ID: <20231213-9d5ad03bed3056007c6e714d@orel> References: <7b633cc441f5133608597463301fef122f5174d3.1702371136.git.haibo1.xu@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <7b633cc441f5133608597463301fef122f5174d3.1702371136.git.haibo1.xu@intel.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231213_060256_806157_C2BD0650 X-CRM114-Status: GOOD ( 16.23 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Dec 12, 2023 at 05:31:14PM +0800, Haibo Xu wrote: > Borrow the cpu_relax() definitions from kernel's > arch/riscv/include/asm/vdso/processor.h to tools/ for riscv. > > Signed-off-by: Haibo Xu > --- > tools/arch/riscv/include/asm/vdso/processor.h | 32 +++++++++++++++++++ > 1 file changed, 32 insertions(+) > create mode 100644 tools/arch/riscv/include/asm/vdso/processor.h > > diff --git a/tools/arch/riscv/include/asm/vdso/processor.h b/tools/arch/riscv/include/asm/vdso/processor.h > new file mode 100644 > index 000000000000..662aca039848 > --- /dev/null > +++ b/tools/arch/riscv/include/asm/vdso/processor.h > @@ -0,0 +1,32 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +#ifndef __ASM_VDSO_PROCESSOR_H > +#define __ASM_VDSO_PROCESSOR_H > + > +#ifndef __ASSEMBLY__ > + > +#include > + > +static inline void cpu_relax(void) > +{ > +#ifdef __riscv_muldiv > + int dummy; > + /* In lieu of a halt instruction, induce a long-latency stall. */ > + __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); > +#endif > + > +#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE > + /* > + * Reduce instruction retirement. > + * This assumes the PC changes. > + */ > + __asm__ __volatile__ ("pause"); > +#else > + /* Encoding of the pause instruction */ > + __asm__ __volatile__ (".4byte 0x100000F"); > +#endif > + barrier(); > +} > + > +#endif /* __ASSEMBLY__ */ > + > +#endif /* __ASM_VDSO_PROCESSOR_H */ > -- > 2.34.1 > Reviewed-by: Andrew Jones _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv