* [PATCH v3 1/3] RISC-V: KVM: set 'vlenb' in kvm_riscv_vcpu_alloc_vector_context()
2023-12-05 17:45 [PATCH v3 0/3] RISC-V, KVM: add 'vlenb' and vector CSRs to get-reg-list Daniel Henrique Barboza
@ 2023-12-05 17:45 ` Daniel Henrique Barboza
2023-12-05 17:45 ` [PATCH v3 2/3] RISC-V: KVM: add 'vlenb' Vector CSR Daniel Henrique Barboza
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Daniel Henrique Barboza @ 2023-12-05 17:45 UTC (permalink / raw)
To: kvm-riscv, linux-riscv, kvm
Cc: anup, atishp, palmer, ajones, Daniel Henrique Barboza
'vlenb', added to riscv_v_ext_state by commit c35f3aa34509 ("RISC-V:
vector: export VLENB csr in __sc_riscv_v_state"), isn't being
initialized in guest_context. If we export 'vlenb' as a KVM CSR,
something we want to do in the next patch, it'll always return 0.
Set 'vlenb' to riscv_v_size/32.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
arch/riscv/kvm/vcpu_vector.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/kvm/vcpu_vector.c b/arch/riscv/kvm/vcpu_vector.c
index b339a2682f25..530e49c588d6 100644
--- a/arch/riscv/kvm/vcpu_vector.c
+++ b/arch/riscv/kvm/vcpu_vector.c
@@ -76,6 +76,7 @@ int kvm_riscv_vcpu_alloc_vector_context(struct kvm_vcpu *vcpu,
cntx->vector.datap = kmalloc(riscv_v_vsize, GFP_KERNEL);
if (!cntx->vector.datap)
return -ENOMEM;
+ cntx->vector.vlenb = riscv_v_vsize / 32;
vcpu->arch.host_context.vector.datap = kzalloc(riscv_v_vsize, GFP_KERNEL);
if (!vcpu->arch.host_context.vector.datap)
--
2.41.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v3 2/3] RISC-V: KVM: add 'vlenb' Vector CSR
2023-12-05 17:45 [PATCH v3 0/3] RISC-V, KVM: add 'vlenb' and vector CSRs to get-reg-list Daniel Henrique Barboza
2023-12-05 17:45 ` [PATCH v3 1/3] RISC-V: KVM: set 'vlenb' in kvm_riscv_vcpu_alloc_vector_context() Daniel Henrique Barboza
@ 2023-12-05 17:45 ` Daniel Henrique Barboza
2023-12-05 17:45 ` [PATCH v3 3/3] RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST Daniel Henrique Barboza
2023-12-14 5:30 ` [PATCH v3 0/3] RISC-V, KVM: add 'vlenb' and vector CSRs to get-reg-list Anup Patel
3 siblings, 0 replies; 6+ messages in thread
From: Daniel Henrique Barboza @ 2023-12-05 17:45 UTC (permalink / raw)
To: kvm-riscv, linux-riscv, kvm
Cc: anup, atishp, palmer, ajones, Daniel Henrique Barboza
Userspace requires 'vlenb' to be able to encode it in reg ID. Otherwise
it is not possible to retrieve any vector reg since we're returning
EINVAL if reg_size isn't vlenb (see kvm_riscv_vcpu_vreg_addr()).
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
arch/riscv/kvm/vcpu_vector.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/riscv/kvm/vcpu_vector.c b/arch/riscv/kvm/vcpu_vector.c
index 530e49c588d6..d92d1348045c 100644
--- a/arch/riscv/kvm/vcpu_vector.c
+++ b/arch/riscv/kvm/vcpu_vector.c
@@ -116,6 +116,9 @@ static int kvm_riscv_vcpu_vreg_addr(struct kvm_vcpu *vcpu,
case KVM_REG_RISCV_VECTOR_CSR_REG(vcsr):
*reg_addr = &cntx->vector.vcsr;
break;
+ case KVM_REG_RISCV_VECTOR_CSR_REG(vlenb):
+ *reg_addr = &cntx->vector.vlenb;
+ break;
case KVM_REG_RISCV_VECTOR_CSR_REG(datap):
default:
return -ENOENT;
@@ -174,6 +177,18 @@ int kvm_riscv_vcpu_set_reg_vector(struct kvm_vcpu *vcpu,
if (!riscv_isa_extension_available(isa, v))
return -ENOENT;
+ if (reg_num == KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)) {
+ struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
+ unsigned long reg_val;
+
+ if (copy_from_user(®_val, uaddr, reg_size))
+ return -EFAULT;
+ if (reg_val != cntx->vector.vlenb)
+ return -EINVAL;
+
+ return 0;
+ }
+
rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, ®_addr);
if (rc)
return rc;
--
2.41.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v3 3/3] RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST
2023-12-05 17:45 [PATCH v3 0/3] RISC-V, KVM: add 'vlenb' and vector CSRs to get-reg-list Daniel Henrique Barboza
2023-12-05 17:45 ` [PATCH v3 1/3] RISC-V: KVM: set 'vlenb' in kvm_riscv_vcpu_alloc_vector_context() Daniel Henrique Barboza
2023-12-05 17:45 ` [PATCH v3 2/3] RISC-V: KVM: add 'vlenb' Vector CSR Daniel Henrique Barboza
@ 2023-12-05 17:45 ` Daniel Henrique Barboza
2023-12-14 7:52 ` Andrew Jones
2023-12-14 5:30 ` [PATCH v3 0/3] RISC-V, KVM: add 'vlenb' and vector CSRs to get-reg-list Anup Patel
3 siblings, 1 reply; 6+ messages in thread
From: Daniel Henrique Barboza @ 2023-12-05 17:45 UTC (permalink / raw)
To: kvm-riscv, linux-riscv, kvm
Cc: anup, atishp, palmer, ajones, Daniel Henrique Barboza
Add all vector CSRs (vstart, vl, vtype, vcsr, vlenb) in get-reg-list.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
arch/riscv/kvm/vcpu_onereg.c | 55 ++++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index f8c9fa0c03c5..2eb4980295ae 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -986,6 +986,55 @@ static int copy_sbi_ext_reg_indices(u64 __user *uindices)
return num_sbi_ext_regs();
}
+static inline unsigned long num_vector_regs(const struct kvm_vcpu *vcpu)
+{
+ if (!riscv_isa_extension_available(vcpu->arch.isa, v))
+ return 0;
+
+ /* vstart, vl, vtype, vcsr, vlenb and 32 vector regs */
+ return 37;
+}
+
+static int copy_vector_reg_indices(const struct kvm_vcpu *vcpu,
+ u64 __user *uindices)
+{
+ const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
+ int n = num_vector_regs(vcpu);
+ u64 reg, size;
+ int i;
+
+ if (n == 0)
+ return 0;
+
+ /* copy vstart, vl, vtype, vcsr and vlenb */
+ size = IS_ENABLED(CONFIG_32BIT) ? KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64;
+ for (i = 0; i < 5; i++) {
+ reg = KVM_REG_RISCV | size | KVM_REG_RISCV_VECTOR | i;
+
+ if (uindices) {
+ if (put_user(reg, uindices))
+ return -EFAULT;
+ uindices++;
+ }
+ }
+
+ /* vector_regs have a variable 'vlenb' size */
+ size = __builtin_ctzl(cntx->vector.vlenb);
+ size <<= KVM_REG_SIZE_SHIFT;
+ for (i = 0; i < 32; i++) {
+ reg = KVM_REG_RISCV | KVM_REG_RISCV_VECTOR | size |
+ KVM_REG_RISCV_VECTOR_REG(i);
+
+ if (uindices) {
+ if (put_user(reg, uindices))
+ return -EFAULT;
+ uindices++;
+ }
+ }
+
+ return n;
+}
+
/*
* kvm_riscv_vcpu_num_regs - how many registers do we present via KVM_GET/SET_ONE_REG
*
@@ -1001,6 +1050,7 @@ unsigned long kvm_riscv_vcpu_num_regs(struct kvm_vcpu *vcpu)
res += num_timer_regs();
res += num_fp_f_regs(vcpu);
res += num_fp_d_regs(vcpu);
+ res += num_vector_regs(vcpu);
res += num_isa_ext_regs(vcpu);
res += num_sbi_ext_regs();
@@ -1045,6 +1095,11 @@ int kvm_riscv_vcpu_copy_reg_indices(struct kvm_vcpu *vcpu,
return ret;
uindices += ret;
+ ret = copy_vector_reg_indices(vcpu, uindices);
+ if (ret < 0)
+ return ret;
+ uindices += ret;
+
ret = copy_isa_ext_reg_indices(vcpu, uindices);
if (ret < 0)
return ret;
--
2.41.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v3 3/3] RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST
2023-12-05 17:45 ` [PATCH v3 3/3] RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST Daniel Henrique Barboza
@ 2023-12-14 7:52 ` Andrew Jones
0 siblings, 0 replies; 6+ messages in thread
From: Andrew Jones @ 2023-12-14 7:52 UTC (permalink / raw)
To: Daniel Henrique Barboza; +Cc: kvm-riscv, linux-riscv, kvm, anup, atishp, palmer
On Tue, Dec 05, 2023 at 02:45:09PM -0300, Daniel Henrique Barboza wrote:
> Add all vector CSRs (vstart, vl, vtype, vcsr, vlenb) in get-reg-list.
We should add another patch for the test for these
(tools/testing/selftests/kvm/riscv/get-reg-list.c)
Thanks,
drew
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> arch/riscv/kvm/vcpu_onereg.c | 55 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
> index f8c9fa0c03c5..2eb4980295ae 100644
> --- a/arch/riscv/kvm/vcpu_onereg.c
> +++ b/arch/riscv/kvm/vcpu_onereg.c
> @@ -986,6 +986,55 @@ static int copy_sbi_ext_reg_indices(u64 __user *uindices)
> return num_sbi_ext_regs();
> }
>
> +static inline unsigned long num_vector_regs(const struct kvm_vcpu *vcpu)
> +{
> + if (!riscv_isa_extension_available(vcpu->arch.isa, v))
> + return 0;
> +
> + /* vstart, vl, vtype, vcsr, vlenb and 32 vector regs */
> + return 37;
> +}
> +
> +static int copy_vector_reg_indices(const struct kvm_vcpu *vcpu,
> + u64 __user *uindices)
> +{
> + const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
> + int n = num_vector_regs(vcpu);
> + u64 reg, size;
> + int i;
> +
> + if (n == 0)
> + return 0;
> +
> + /* copy vstart, vl, vtype, vcsr and vlenb */
> + size = IS_ENABLED(CONFIG_32BIT) ? KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64;
> + for (i = 0; i < 5; i++) {
> + reg = KVM_REG_RISCV | size | KVM_REG_RISCV_VECTOR | i;
> +
> + if (uindices) {
> + if (put_user(reg, uindices))
> + return -EFAULT;
> + uindices++;
> + }
> + }
> +
> + /* vector_regs have a variable 'vlenb' size */
> + size = __builtin_ctzl(cntx->vector.vlenb);
> + size <<= KVM_REG_SIZE_SHIFT;
> + for (i = 0; i < 32; i++) {
> + reg = KVM_REG_RISCV | KVM_REG_RISCV_VECTOR | size |
> + KVM_REG_RISCV_VECTOR_REG(i);
> +
> + if (uindices) {
> + if (put_user(reg, uindices))
> + return -EFAULT;
> + uindices++;
> + }
> + }
> +
> + return n;
> +}
> +
> /*
> * kvm_riscv_vcpu_num_regs - how many registers do we present via KVM_GET/SET_ONE_REG
> *
> @@ -1001,6 +1050,7 @@ unsigned long kvm_riscv_vcpu_num_regs(struct kvm_vcpu *vcpu)
> res += num_timer_regs();
> res += num_fp_f_regs(vcpu);
> res += num_fp_d_regs(vcpu);
> + res += num_vector_regs(vcpu);
> res += num_isa_ext_regs(vcpu);
> res += num_sbi_ext_regs();
>
> @@ -1045,6 +1095,11 @@ int kvm_riscv_vcpu_copy_reg_indices(struct kvm_vcpu *vcpu,
> return ret;
> uindices += ret;
>
> + ret = copy_vector_reg_indices(vcpu, uindices);
> + if (ret < 0)
> + return ret;
> + uindices += ret;
> +
> ret = copy_isa_ext_reg_indices(vcpu, uindices);
> if (ret < 0)
> return ret;
> --
> 2.41.0
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3 0/3] RISC-V, KVM: add 'vlenb' and vector CSRs to get-reg-list
2023-12-05 17:45 [PATCH v3 0/3] RISC-V, KVM: add 'vlenb' and vector CSRs to get-reg-list Daniel Henrique Barboza
` (2 preceding siblings ...)
2023-12-05 17:45 ` [PATCH v3 3/3] RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST Daniel Henrique Barboza
@ 2023-12-14 5:30 ` Anup Patel
3 siblings, 0 replies; 6+ messages in thread
From: Anup Patel @ 2023-12-14 5:30 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: kvm-riscv, linux-riscv, kvm, atishp, palmer, ajones
On Tue, Dec 5, 2023 at 11:15 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> In this version we're exporting all vector regs, not just vector CSRs,
> in get-reg-list. All changes were done in patch 3.
>
> No other changes made.
>
> Changes from v2:
> - patch 3:
> - check num_vector_regs() != 0 before copying vector regs
> - export all 32 vector regs in num_vector_regs() and copy_vector_reg_indices()
> - initialize 'size' out of the loop in copy_vector_reg_indices()
> - v2 link: https://lore.kernel.org/kvm/20231205135041.2208004-1-dbarboza@ventanamicro.com/
>
> Daniel Henrique Barboza (3):
> RISC-V: KVM: set 'vlenb' in kvm_riscv_vcpu_alloc_vector_context()
> RISC-V: KVM: add 'vlenb' Vector CSR
> RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST
Reviewed-by: Anup Patel <anup@brainfault.org>
I have improved subject and description of patch3 at time of merging
this series.
Queued this series for Linux-6.8
Thanks,
Anup
>
> arch/riscv/kvm/vcpu_onereg.c | 55 ++++++++++++++++++++++++++++++++++++
> arch/riscv/kvm/vcpu_vector.c | 16 +++++++++++
> 2 files changed, 71 insertions(+)
>
> --
> 2.41.0
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread