From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com
Cc: greentime.hu@sifive.com, guoren@linux.alibaba.com,
bjorn@kernel.org, charlie@rivosinc.com, ardb@kernel.org,
arnd@arndb.de, Andy Chiu <andy.chiu@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Vincent Chen <vincent.chen@sifive.com>,
Conor Dooley <conor.dooley@microchip.com>
Subject: [v5, 2/6] riscv: vector: make Vector always available for softirq context
Date: Thu, 14 Dec 2023 15:57:17 +0000 [thread overview]
Message-ID: <20231214155721.1753-3-andy.chiu@sifive.com> (raw)
In-Reply-To: <20231214155721.1753-1-andy.chiu@sifive.com>
By disabling bottom halves in active kerne-mode Vector, softirq will not
be able to nest on top of any kernel-mode Vector.
After this patch, Vector context cannot start with irqs disabled.
Otherwise local_bh_enable() may run in a wrong context.
Disabling bh is not enough for RT-kernel to prevent preeemption. So
we must disable preemption, which also implies disabling bh on RT.
Related-to: commit 696207d4258b ("arm64/sve: Make kernel FPU protection RT friendly")
Related-to: commit 66c3ec5a7120 ("arm64: neon: Forbid when irqs are disabled")
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
---
Changelog v4:
- new patch since v4
---
arch/riscv/include/asm/simd.h | 6 +++++-
arch/riscv/kernel/kernel_mode_vector.c | 10 ++++++++--
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/include/asm/simd.h b/arch/riscv/include/asm/simd.h
index 269752bfa2cc..cd6180fe37c0 100644
--- a/arch/riscv/include/asm/simd.h
+++ b/arch/riscv/include/asm/simd.h
@@ -26,8 +26,12 @@ static __must_check inline bool may_use_simd(void)
/*
* RISCV_KERNEL_MODE_V is only set while preemption is disabled,
* and is clear whenever preemption is enabled.
+ *
+ * Kernel-mode Vector temperarily disables bh. So we must not return
+ * true on irq_disabled(). Otherwise we would fail the lockdep check
+ * calling local_bh_enable()
*/
- return !in_hardirq() && !in_nmi() && !(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK);
+ return !in_hardirq() && !in_nmi() && !irqs_disabled() && !(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK);
}
#else /* ! CONFIG_RISCV_ISA_V */
diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/kernel_mode_vector.c
index c9ccf21dd16c..52e42f74ec9a 100644
--- a/arch/riscv/kernel/kernel_mode_vector.c
+++ b/arch/riscv/kernel/kernel_mode_vector.c
@@ -23,7 +23,10 @@
*/
void get_cpu_vector_context(void)
{
- preempt_disable();
+ if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+ local_bh_disable();
+ else
+ preempt_disable();
WARN_ON(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK);
riscv_v_ctx_cnt_add(RISCV_KERNEL_MODE_V);
@@ -41,7 +44,10 @@ void put_cpu_vector_context(void)
WARN_ON(!(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK));
riscv_v_ctx_cnt_sub(RISCV_KERNEL_MODE_V);
- preempt_enable();
+ if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+ local_bh_enable();
+ else
+ preempt_enable();
}
/*
--
2.17.1
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next prev parent reply other threads:[~2023-12-14 15:58 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-14 15:57 [v5, 0/6] riscv: support kernel-mode Vector Andy Chiu
2023-12-14 15:57 ` [v5, 1/6] riscv: Add support for kernel mode vector Andy Chiu
2023-12-15 6:24 ` Charlie Jenkins
2023-12-15 16:01 ` Andy Chiu
2023-12-15 18:41 ` Charlie Jenkins
2023-12-19 6:04 ` Andy Chiu
2023-12-14 15:57 ` Andy Chiu [this message]
2023-12-14 15:57 ` [v5, 3/6] riscv: Add vector extension XOR implementation Andy Chiu
2023-12-14 15:57 ` [v5, 4/6] riscv: sched: defer restoring Vector context for user Andy Chiu
2023-12-14 15:57 ` [v5, 5/6] riscv: lib: vectorize copy_to_user/copy_from_user Andy Chiu
2023-12-15 6:25 ` Charlie Jenkins
2023-12-15 13:52 ` Andrew Jones
2023-12-19 14:43 ` Andy Chiu
2023-12-19 9:58 ` Andy Chiu
2023-12-14 15:57 ` [v5, 6/6] riscv: lib: add vectorized mem* routines Andy Chiu
2023-12-15 19:56 ` Charlie Jenkins
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