From: Andrew Jones <ajones@ventanamicro.com>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Atish Patra <atishp@atishpatra.org>,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
virtualization@lists.linux-foundation.org, anup@brainfault.org,
pbonzini@redhat.com, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu, jgross@suse.com,
srivatsa@csail.mit.edu, guoren@kernel.org,
conor.dooley@microchip.com
Subject: Re: [PATCH v3 07/13] RISC-V: KVM: Add support for SBI extension registers
Date: Wed, 20 Dec 2023 07:32:10 +0100 [thread overview]
Message-ID: <20231220-b68357fb121f79bec9dd1a24@orel> (raw)
In-Reply-To: <CAK9=C2XQb3=PbU+Ggpp1jEnDbc-DER+eEY9j=w8w=_6DNjcdDg@mail.gmail.com>
On Wed, Dec 20, 2023 at 11:49:46AM +0530, Anup Patel wrote:
> On Wed, Dec 20, 2023 at 1:28 AM Atish Patra <atishp@atishpatra.org> wrote:
> >
> > On Sun, Dec 17, 2023 at 12:40 PM Andrew Jones <ajones@ventanamicro.com> wrote:
> > >
> > > Some SBI extensions have state that needs to be saved / restored
> > > when migrating the VM. Provide a get/set-one-reg register type
> > > for SBI extension registers. Each SBI extension that uses this type
> > > will have its own subtype. There are currently no subtypes defined.
> > > The next patch introduces the first one.
> > >
> > > Reviewed-by: Anup Patel <anup@brainfault.org>
> > > Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> > > ---
> > > arch/riscv/include/asm/kvm_vcpu_sbi.h | 4 ++
> > > arch/riscv/include/uapi/asm/kvm.h | 3 ++
> > > arch/riscv/kvm/vcpu_onereg.c | 42 +++++++++++++++++--
> > > arch/riscv/kvm/vcpu_sbi.c | 58 +++++++++++++++++++++++++++
> > > 4 files changed, 103 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h
> > > index 99c23bb37a37..dd60f73b5c36 100644
> > > --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h
> > > +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h
> > > @@ -60,6 +60,10 @@ int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu,
> > > const struct kvm_one_reg *reg);
> > > int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu,
> > > const struct kvm_one_reg *reg);
> > > +int kvm_riscv_vcpu_set_reg_sbi(struct kvm_vcpu *vcpu,
> > > + const struct kvm_one_reg *reg);
> > > +int kvm_riscv_vcpu_get_reg_sbi(struct kvm_vcpu *vcpu,
> > > + const struct kvm_one_reg *reg);
> > > const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(
> > > struct kvm_vcpu *vcpu, unsigned long extid);
> > > bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, int idx);
> > > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> > > index e961d79622fb..30f89a0e855f 100644
> > > --- a/arch/riscv/include/uapi/asm/kvm.h
> > > +++ b/arch/riscv/include/uapi/asm/kvm.h
> > > @@ -242,6 +242,9 @@ enum KVM_RISCV_SBI_EXT_ID {
> > > #define KVM_REG_RISCV_VECTOR_REG(n) \
> > > ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long))
> > >
> > > +/* Registers for specific SBI extensions are mapped as type 10 */
> > > +#define KVM_REG_RISCV_SBI (0x0a << KVM_REG_RISCV_TYPE_SHIFT)
> > > +
> >
> >
> > nit comment: KVM_REG_RISCV_SBI looks bit odd when we already have
> > KVM_REG_RISCV_SBI_EXT for
> > extension enabling/disabling.
> >
> > How about renaming this to KVM_REG_RISCV_SBI_EXT_STATE or something
> > similar indicate that this
> > for a specific extension state ?
>
> How about KVM_REG_RISCV_SBI_STATE ?
Also works for me.
Thanks,
drew
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next prev parent reply other threads:[~2023-12-20 6:32 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-17 20:40 [PATCH v3 00/13] RISC-V: Add steal-time support Andrew Jones
2023-12-17 20:40 ` [PATCH v3 01/13] RISC-V: paravirt: Add skeleton for pv-time support Andrew Jones
2023-12-19 0:48 ` Atish Patra
2023-12-19 14:29 ` Andrew Jones
2023-12-17 20:40 ` [PATCH v3 02/13] RISC-V: Add SBI STA extension definitions Andrew Jones
2023-12-19 0:49 ` Atish Patra
2023-12-17 20:40 ` [PATCH v3 03/13] RISC-V: paravirt: Implement steal-time support Andrew Jones
2023-12-19 1:41 ` Atish Patra
2023-12-20 6:41 ` Anup Patel
2023-12-17 20:40 ` [PATCH v3 04/13] RISC-V: KVM: Add SBI STA extension skeleton Andrew Jones
2023-12-19 1:42 ` Atish Patra
2023-12-17 20:40 ` [PATCH v3 05/13] RISC-V: KVM: Add steal-update vcpu request Andrew Jones
2023-12-19 1:46 ` Atish Patra
2023-12-17 20:40 ` [PATCH v3 06/13] RISC-V: KVM: Add SBI STA info to vcpu_arch Andrew Jones
2023-12-19 1:49 ` Atish Patra
2023-12-17 20:40 ` [PATCH v3 07/13] RISC-V: KVM: Add support for SBI extension registers Andrew Jones
2023-12-19 19:58 ` Atish Patra
2023-12-20 6:16 ` Andrew Jones
2023-12-20 6:19 ` Anup Patel
2023-12-20 6:32 ` Andrew Jones [this message]
2023-12-17 20:40 ` [PATCH v3 08/13] RISC-V: KVM: Add support for SBI STA registers Andrew Jones
2023-12-17 20:40 ` [PATCH v3 09/13] RISC-V: KVM: Implement SBI STA extension Andrew Jones
2023-12-19 21:52 ` Atish Patra
2023-12-17 20:40 ` [PATCH v3 10/13] RISC-V: KVM: selftests: Move sbi_ecall to processor.c Andrew Jones
2023-12-17 20:40 ` [PATCH v3 11/13] RISC-V: KVM: selftests: Add guest_sbi_probe_extension Andrew Jones
2023-12-19 21:57 ` Atish Patra
2023-12-20 6:28 ` Andrew Jones
2023-12-17 20:40 ` [PATCH v3 12/13] RISC-V: KVM: selftests: Add steal_time test support Andrew Jones
2023-12-19 23:39 ` Atish Patra
2023-12-17 20:40 ` [PATCH v3 13/13] RISC-V: KVM: selftests: Add get-reg-list test for STA registers Andrew Jones
2023-12-19 23:40 ` Atish Patra
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