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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id iv13-20020a05600c548d00b0040d30af488asm49891379wmb.40.2024.01.02.07.39.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 07:39:07 -0800 (PST) Date: Tue, 2 Jan 2024 16:39:06 +0100 From: Andrew Jones To: Sia Jee Heng Subject: Re: [RFC v1 1/1] RISC-V: ACPI: Enable SPCR table for console output on RISC-V Message-ID: <20240102-1ddc9ec273fded1548ee586d@orel> References: <20231229065405.235625-1-jeeheng.sia@starfivetech.com> <20231229065405.235625-2-jeeheng.sia@starfivetech.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20231229065405.235625-2-jeeheng.sia@starfivetech.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240102_073910_927504_AC423252 X-CRM114-Status: GOOD ( 20.22 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aou@eecs.berkeley.edu, rafael.j.wysocki@intel.com, linux-kernel@vger.kernel.org, conor.dooley@microchip.com, palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Dec 29, 2023 at 02:54:05PM +0800, Sia Jee Heng wrote: > The ACPI SPCR code has been used to enable console output for ARM64 and > X86. The same code can be reused for RISC-V. > > Vendor will enable/disable the SPCR table in the firmware based on the > platform design. However, in cases where the SPCR table is not usable, > a kernel parameter could be used to specify the preferred console. > > Signed-off-by: Sia Jee Heng > --- > arch/riscv/kernel/acpi.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c > index e619edc8b0cc..5ec2fdf9e09f 100644 > --- a/arch/riscv/kernel/acpi.c > +++ b/arch/riscv/kernel/acpi.c > @@ -18,6 +18,7 @@ > #include > #include > #include > +#include > > int acpi_noirq = 1; /* skip ACPI IRQ initialization */ > int acpi_disabled = 1; > @@ -151,6 +152,9 @@ void __init acpi_boot_table_init(void) > if (!param_acpi_force) > disable_acpi(); > } > + > + if (!acpi_disabled) > + acpi_parse_spcr(earlycon_acpi_spcr_enable, true); Both arm64 and loongarch call early_init_dt_scan_chosen_stdout() when acpi_disabled and earlycon_acpi_spcr_enable are both true. Is that not necessary for RISC-V? Thanks, drew > } > > static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end) > -- > 2.34.1 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv