From: Andrew Jones <ajones@ventanamicro.com>
To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org
Cc: anup@brainfault.org, atishp@atishpatra.org,
paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, kernel test robot <lkp@intel.com>
Subject: [PATCH 2/3] RISC-V: paravirt: Use correct restricted types
Date: Wed, 31 Jan 2024 13:05:14 +0100 [thread overview]
Message-ID: <20240131120511.200338-7-ajones@ventanamicro.com> (raw)
In-Reply-To: <20240131120511.200338-5-ajones@ventanamicro.com>
__le32 and __le64 types should be used with le32_to_cpu() and
le64_to_cpu(), as sparse helpfully points out.
Fixes: fdf68acccfc6 ("RISC-V: paravirt: Implement steal-time support")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202401011933.hL9zqmKo-lkp@intel.com/
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
---
arch/riscv/kernel/paravirt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/kernel/paravirt.c b/arch/riscv/kernel/paravirt.c
index 15c5d4048db5..0d6225fd3194 100644
--- a/arch/riscv/kernel/paravirt.c
+++ b/arch/riscv/kernel/paravirt.c
@@ -91,8 +91,8 @@ static int pv_time_cpu_down_prepare(unsigned int cpu)
static u64 pv_time_steal_clock(int cpu)
{
struct sbi_sta_struct *st = per_cpu_ptr(&steal_time, cpu);
- u32 sequence;
- u64 steal;
+ __le32 sequence;
+ __le64 steal;
/*
* Check the sequence field before and after reading the steal
--
2.43.0
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next prev parent reply other threads:[~2024-01-31 12:05 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-31 12:05 [PATCH 0/3] RISC-V: Fix sparse warnings Andrew Jones
2024-01-31 12:05 ` [PATCH 1/3] RISC-V: paravirt: steal_time should be static Andrew Jones
2024-01-31 19:44 ` Atish Patra
2024-01-31 12:05 ` Andrew Jones [this message]
2024-01-31 19:45 ` [PATCH 2/3] RISC-V: paravirt: Use correct restricted types Atish Patra
2024-01-31 12:05 ` [PATCH 3/3] RISC-V: KVM: " Andrew Jones
2024-01-31 19:46 ` Atish Patra
2024-02-02 15:57 ` [PATCH 0/3] RISC-V: Fix sparse warnings Anup Patel
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