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From: Conor Dooley <conor@kernel.org>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Stefan O'Rear <sorear@fastmail.com>
Subject: Re: [PATCH -fixes v2 2/4] dt-bindings: riscv: Add ratified privileged ISA versions
Date: Tue, 13 Feb 2024 17:07:29 +0000	[thread overview]
Message-ID: <20240213-cilantro-operator-acbf40493bbd@spud> (raw)
In-Reply-To: <20240213-limping-ether-adbdc205ebc6@spud>


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On Tue, Feb 13, 2024 at 05:03:46PM +0000, Conor Dooley wrote:
> On Mon, Feb 12, 2024 at 07:37:33PM -0800, Samuel Holland wrote:
> > The baseline for the RISC-V privileged ISA is version 1.10. Using
> > features from newer versions of the privileged ISA requires the
> > supported version to be reported by platform firmware, either in the ISA
> > string (where the binding already accepts version numbers) or in the
> > riscv,isa-extensions property. So far two newer versions are ratified.
> > 
> > Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> > ---
> > 
> > Changes in v2:
> >  - New patch for v2
> > 
> >  .../devicetree/bindings/riscv/extensions.yaml | 20 +++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > index 63d81dc895e5..7faf22df01af 100644
> > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > @@ -121,6 +121,16 @@ properties:
> >              version of the privileged ISA specification.
> >  
> >          # multi-letter extensions, sorted alphanumerically
> 
> > +        - const: sm1p11
> 
> Why are we beholden to this "1p11" format of RVI's? We have free choice
> of characters here, what's stopping us using "machine-v1.11", for
> example?

We could also choose to communicate this using a specific property, but
I have not really thought that one through yet.

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  reply	other threads:[~2024-02-13 17:07 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-13  3:37 [PATCH -fixes v2 0/4] riscv: cbo.zero fixes Samuel Holland
2024-02-13  3:37 ` [PATCH -fixes v2 1/4] riscv: Fix enabling cbo.zero when running in M-mode Samuel Holland
2024-02-13  3:37 ` [PATCH -fixes v2 2/4] dt-bindings: riscv: Add ratified privileged ISA versions Samuel Holland
2024-02-13  8:50   ` Krzysztof Kozlowski
2024-02-13 14:25   ` Andrew Jones
2024-02-15 13:14     ` Conor Dooley
2024-02-16 15:41       ` Stefan O'Rear
2024-02-13 17:03   ` Conor Dooley
2024-02-13 17:07     ` Conor Dooley [this message]
2024-02-13 17:42     ` Stefan O'Rear
2024-02-13 18:00       ` Samuel Holland
2024-02-13  3:37 ` [PATCH -fixes v2 3/4] riscv: Add ISA extension parsing for Sm and Ss Samuel Holland
2024-02-13 15:14   ` Andrew Jones
2024-02-13 17:52     ` Stefan O'Rear
2024-02-13 18:18       ` Samuel Holland
2024-02-13 18:07   ` Conor Dooley
2024-02-13 20:22     ` Samuel Holland
2024-02-13 20:43       ` Stefan O'Rear
2024-02-13 23:15         ` Conor Dooley
2024-02-18 15:00           ` Samuel Holland
2024-02-18 17:02             ` Conor Dooley
2024-02-13  3:37 ` [PATCH -fixes v2 4/4] riscv: Save/restore envcfg CSR during CPU suspend Samuel Holland
2024-02-13 14:49   ` Andrew Jones
2024-02-13 17:53     ` Stefan O'Rear
2024-02-18 14:09       ` Samuel Holland

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