From: Conor Dooley <conor@kernel.org>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: Samuel Holland <samuel.holland@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Stefan O'Rear <sorear@fastmail.com>
Subject: Re: [PATCH -fixes v2 2/4] dt-bindings: riscv: Add ratified privileged ISA versions
Date: Thu, 15 Feb 2024 13:14:26 +0000 [thread overview]
Message-ID: <20240215-icy-oblong-67adb68a4074@spud> (raw)
In-Reply-To: <20240213-88c9d65fd2b6465fc4793f56@orel>
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On Tue, Feb 13, 2024 at 03:25:44PM +0100, Andrew Jones wrote:
> On Mon, Feb 12, 2024 at 07:37:33PM -0800, Samuel Holland wrote:
> Note, QEMU doesn't add these extensions to the ISA string yet, but I think
> it should start, particularly the profile CPU types which should ensure
> all the profile's mandatory extensions are added to the ISA string in
> order to avoid any confusion.
Something to note about these "mandatory extensions" that are names for
things we already assumed were present - they're utterly useless and any
DT property should note their absence, not presence, in order to be of any
use. Anything parsing a DT cannot see "svbare" and gain any new
information, since the lack of it could be something that predates the
definition of "svbare" or something without "svbare".
Shit, but that's exactly why I deprecated riscv,isa.
Cheers,
Conor.
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next prev parent reply other threads:[~2024-02-15 13:14 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-13 3:37 [PATCH -fixes v2 0/4] riscv: cbo.zero fixes Samuel Holland
2024-02-13 3:37 ` [PATCH -fixes v2 1/4] riscv: Fix enabling cbo.zero when running in M-mode Samuel Holland
2024-02-13 3:37 ` [PATCH -fixes v2 2/4] dt-bindings: riscv: Add ratified privileged ISA versions Samuel Holland
2024-02-13 8:50 ` Krzysztof Kozlowski
2024-02-13 14:25 ` Andrew Jones
2024-02-15 13:14 ` Conor Dooley [this message]
2024-02-16 15:41 ` Stefan O'Rear
2024-02-13 17:03 ` Conor Dooley
2024-02-13 17:07 ` Conor Dooley
2024-02-13 17:42 ` Stefan O'Rear
2024-02-13 18:00 ` Samuel Holland
2024-02-13 3:37 ` [PATCH -fixes v2 3/4] riscv: Add ISA extension parsing for Sm and Ss Samuel Holland
2024-02-13 15:14 ` Andrew Jones
2024-02-13 17:52 ` Stefan O'Rear
2024-02-13 18:18 ` Samuel Holland
2024-02-13 18:07 ` Conor Dooley
2024-02-13 20:22 ` Samuel Holland
2024-02-13 20:43 ` Stefan O'Rear
2024-02-13 23:15 ` Conor Dooley
2024-02-18 15:00 ` Samuel Holland
2024-02-18 17:02 ` Conor Dooley
2024-02-13 3:37 ` [PATCH -fixes v2 4/4] riscv: Save/restore envcfg CSR during CPU suspend Samuel Holland
2024-02-13 14:49 ` Andrew Jones
2024-02-13 17:53 ` Stefan O'Rear
2024-02-18 14:09 ` Samuel Holland
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