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From: Conor Dooley <conor.dooley@microchip.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 4/4] riscv: Allow NOMMU kernels to run in S-mode
Date: Tue, 27 Feb 2024 12:24:09 +0000	[thread overview]
Message-ID: <20240227-seventh-overgrown-2fa453e8a775@wendy> (raw)
In-Reply-To: <20240227003630.3634533-5-samuel.holland@sifive.com>


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On Mon, Feb 26, 2024 at 04:34:49PM -0800, Samuel Holland wrote:
> For ease of testing, it is convenient to run NOMMU kernels in supervisor
> mode. The only required change is to offset the kernel load address,
> since the beginning of RAM is usually reserved for M-mode firmware.
> 
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
> 
>  arch/riscv/Kconfig | 15 ++++++++++-----
>  1 file changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index ef53c00470d6..0dc09b2ac2f6 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -64,7 +64,7 @@ config RISCV
>  	select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE
>  	select BINFMT_FLAT_NO_DATA_START_OFFSET if !MMU
>  	select BUILDTIME_TABLE_SORT if MMU
> -	select CLINT_TIMER if !MMU
> +	select CLINT_TIMER if RISCV_M_MODE
>  	select CLONE_BACKWARDS
>  	select COMMON_CLK
>  	select CPU_PM if CPU_IDLE || HIBERNATION || SUSPEND
> @@ -220,8 +220,12 @@ config ARCH_MMAP_RND_COMPAT_BITS_MAX
>  
>  # set if we run in machine mode, cleared if we run in supervisor mode
>  config RISCV_M_MODE
> -	bool
> -	default !MMU
> +	bool "Build a kernel that runs in machine mode"
> +	depends on !MMU
> +	default y
> +	help
> +	  Select this option if you want to run the kernel in M-mode,
> +	  without the assistance of any other firmware.
>  
>  # set if we are running in S-mode and can use SBI calls
>  config RISCV_SBI
> @@ -238,8 +242,9 @@ config MMU
>  
>  config PAGE_OFFSET
>  	hex
> -	default 0xC0000000 if 32BIT && MMU
> -	default 0x80000000 if !MMU
> +	default 0x80000000 if !MMU && RISCV_M_MODE
> +	default 0x80200000 if !MMU
> +	default 0xc0000000 if 32BIT
>  	default 0xff60000000000000 if 64BIT

The first default seen with a passing condition is the default chosen,
right?

Cheers,
Conor.

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  reply	other threads:[~2024-02-27 12:25 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-27  0:34 [PATCH 0/4] riscv: 64-bit NOMMU fixes and enhancements Samuel Holland
2024-02-27  0:34 ` [PATCH 1/4] riscv: Fix TASK_SIZE on 64-bit NOMMU Samuel Holland
2024-03-27  7:04   ` Jisheng Zhang
2024-03-27  7:54     ` Bo Gan
2024-02-27  0:34 ` [PATCH 2/4] riscv: Fix loading 64-bit NOMMU kernels past the start of RAM Samuel Holland
2024-02-27 12:18   ` Conor Dooley
2024-02-27 19:22     ` Samuel Holland
2024-02-28 15:37       ` Conor Dooley
2024-02-27  0:34 ` [PATCH 3/4] riscv: Remove MMU dependency from Zbb and Zicboz Samuel Holland
2024-02-27 11:51   ` Conor Dooley
2024-02-27  0:34 ` [PATCH 4/4] riscv: Allow NOMMU kernels to run in S-mode Samuel Holland
2024-02-27 12:24   ` Conor Dooley [this message]
2024-02-27 19:02     ` Samuel Holland
2024-02-28 15:21       ` Conor Dooley
2024-02-27 12:13 ` [PATCH 0/4] riscv: 64-bit NOMMU fixes and enhancements Conor Dooley
2024-02-27 18:51   ` Samuel Holland
2024-04-10 14:00 ` patchwork-bot+linux-riscv
2024-04-10 14:20 ` patchwork-bot+linux-riscv

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