* [PATCH v1 1/2] RISC-V: drop SOC_SIFIVE for ARCH_SIFIVE
@ 2024-03-05 18:37 Conor Dooley
2024-03-05 18:37 ` [PATCH v1 2/2] RISC-V: drop SOC_VIRT for ARCH_VIRT Conor Dooley
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Conor Dooley @ 2024-03-05 18:37 UTC (permalink / raw)
To: linux-riscv
Cc: conor, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
linux-kernel
From: Conor Dooley <conor.dooley@microchip.com>
All the users in the kernel are gone and generated .config files from
previous LTS kernels will contain ARCH_SIFIVE. Drop SOC_SIFIVE and
update the defconfig.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
CC: Paul Walmsley <paul.walmsley@sifive.com>
CC: Palmer Dabbelt <palmer@dabbelt.com>
CC: Albert Ou <aou@eecs.berkeley.edu>
CC: linux-riscv@lists.infradead.org
CC: linux-kernel@vger.kernel.org
---
arch/riscv/Kconfig.socs | 3 ---
arch/riscv/configs/defconfig | 2 +-
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index e08e91c49abe..e85ffb63c48d 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -14,9 +14,6 @@ config ARCH_RENESAS
This enables support for the RISC-V based Renesas SoCs.
config ARCH_SIFIVE
- def_bool SOC_SIFIVE
-
-config SOC_SIFIVE
bool "SiFive SoCs"
select ERRATA_SIFIVE if !XIP_KERNEL
help
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 89a009a580fe..ab3bab313d56 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -27,7 +27,7 @@ CONFIG_EXPERT=y
CONFIG_PROFILING=y
CONFIG_SOC_MICROCHIP_POLARFIRE=y
CONFIG_ARCH_RENESAS=y
-CONFIG_SOC_SIFIVE=y
+CONFIG_ARCH_SIFIVE=y
CONFIG_ARCH_SOPHGO=y
CONFIG_SOC_STARFIVE=y
CONFIG_ARCH_SUNXI=y
--
2.43.0
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linux-riscv@lists.infradead.org
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v1 2/2] RISC-V: drop SOC_VIRT for ARCH_VIRT 2024-03-05 18:37 [PATCH v1 1/2] RISC-V: drop SOC_SIFIVE for ARCH_SIFIVE Conor Dooley @ 2024-03-05 18:37 ` Conor Dooley 2024-04-03 18:22 ` Palmer Dabbelt 2024-03-12 4:34 ` [PATCH v1 1/2] RISC-V: drop SOC_SIFIVE for ARCH_SIFIVE Samuel Holland ` (2 subsequent siblings) 3 siblings, 1 reply; 6+ messages in thread From: Conor Dooley @ 2024-03-05 18:37 UTC (permalink / raw) To: linux-riscv Cc: conor, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-kernel, Brendan Higgins, David Gow, Rae Moar, Jason A. Donenfeld, Shuah Khan, linux-kselftest, kunit-dev, wireguard, netdev From: Conor Dooley <conor.dooley@microchip.com> The ARCH_ and SOC_ versions of this symbol have persisted for quite a while now in parallel. Generated .config files from previous LTS kernels should have both. Finally remove SOC_VIRT and update all config files using it. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- I had a 1.5 year old ack from Jason that I dropped due to the passage of time. CC: Paul Walmsley <paul.walmsley@sifive.com> CC: Palmer Dabbelt <palmer@dabbelt.com> CC: Albert Ou <aou@eecs.berkeley.edu> CC: Brendan Higgins <brendan.higgins@linux.dev> CC: David Gow <davidgow@google.com> CC: Rae Moar <rmoar@google.com> CC: "Jason A. Donenfeld" <Jason@zx2c4.com> CC: Shuah Khan <shuah@kernel.org> CC: linux-riscv@lists.infradead.org CC: linux-kernel@vger.kernel.org CC: linux-kselftest@vger.kernel.org CC: kunit-dev@googlegroups.com CC: wireguard@lists.zx2c4.com CC: netdev@vger.kernel.org --- arch/riscv/Kconfig.socs | 3 --- arch/riscv/configs/defconfig | 2 +- arch/riscv/configs/nommu_virt_defconfig | 2 +- tools/testing/kunit/qemu_configs/riscv.py | 2 +- tools/testing/selftests/wireguard/qemu/arch/riscv32.config | 2 +- tools/testing/selftests/wireguard/qemu/arch/riscv64.config | 2 +- 6 files changed, 5 insertions(+), 8 deletions(-) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index e85ffb63c48d..dcbfb659839c 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -52,9 +52,6 @@ config ARCH_THEAD This enables support for the RISC-V based T-HEAD SoCs. config ARCH_VIRT - def_bool SOC_VIRT - -config SOC_VIRT bool "QEMU Virt Machine" select CLINT_TIMER if RISCV_M_MODE select POWER_RESET diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index ab3bab313d56..8d46a9137b1e 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -32,7 +32,7 @@ CONFIG_ARCH_SOPHGO=y CONFIG_SOC_STARFIVE=y CONFIG_ARCH_SUNXI=y CONFIG_ARCH_THEAD=y -CONFIG_SOC_VIRT=y +CONFIG_ARCH_VIRT=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y CONFIG_PM=y diff --git a/arch/riscv/configs/nommu_virt_defconfig b/arch/riscv/configs/nommu_virt_defconfig index b794e2f8144e..de8143d1f738 100644 --- a/arch/riscv/configs/nommu_virt_defconfig +++ b/arch/riscv/configs/nommu_virt_defconfig @@ -24,7 +24,7 @@ CONFIG_EXPERT=y CONFIG_SLUB=y CONFIG_SLUB_TINY=y # CONFIG_MMU is not set -CONFIG_SOC_VIRT=y +CONFIG_ARCH_VIRT=y CONFIG_NONPORTABLE=y CONFIG_SMP=y CONFIG_CMDLINE="root=/dev/vda rw earlycon=uart8250,mmio,0x10000000,115200n8 console=ttyS0" diff --git a/tools/testing/kunit/qemu_configs/riscv.py b/tools/testing/kunit/qemu_configs/riscv.py index 12a1d525978a..c87758030ff7 100644 --- a/tools/testing/kunit/qemu_configs/riscv.py +++ b/tools/testing/kunit/qemu_configs/riscv.py @@ -13,7 +13,7 @@ if not os.path.isfile(OPENSBI_PATH): QEMU_ARCH = QemuArchParams(linux_arch='riscv', kconfig=''' -CONFIG_SOC_VIRT=y +CONFIG_ARCH_VIRT=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y diff --git a/tools/testing/selftests/wireguard/qemu/arch/riscv32.config b/tools/testing/selftests/wireguard/qemu/arch/riscv32.config index 2fc36efb166d..2500eaa9b469 100644 --- a/tools/testing/selftests/wireguard/qemu/arch/riscv32.config +++ b/tools/testing/selftests/wireguard/qemu/arch/riscv32.config @@ -2,7 +2,7 @@ CONFIG_NONPORTABLE=y CONFIG_ARCH_RV32I=y CONFIG_MMU=y CONFIG_FPU=y -CONFIG_SOC_VIRT=y +CONFIG_ARCH_VIRT=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y diff --git a/tools/testing/selftests/wireguard/qemu/arch/riscv64.config b/tools/testing/selftests/wireguard/qemu/arch/riscv64.config index dc266f3b1915..29a67ac67766 100644 --- a/tools/testing/selftests/wireguard/qemu/arch/riscv64.config +++ b/tools/testing/selftests/wireguard/qemu/arch/riscv64.config @@ -1,7 +1,7 @@ CONFIG_ARCH_RV64I=y CONFIG_MMU=y CONFIG_FPU=y -CONFIG_SOC_VIRT=y +CONFIG_ARCH_VIRT=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y -- 2.43.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v1 2/2] RISC-V: drop SOC_VIRT for ARCH_VIRT 2024-03-05 18:37 ` [PATCH v1 2/2] RISC-V: drop SOC_VIRT for ARCH_VIRT Conor Dooley @ 2024-04-03 18:22 ` Palmer Dabbelt 0 siblings, 0 replies; 6+ messages in thread From: Palmer Dabbelt @ 2024-04-03 18:22 UTC (permalink / raw) To: Conor Dooley Cc: linux-riscv, Conor Dooley, Conor Dooley, Paul Walmsley, aou, linux-kernel, brendan.higgins, davidgow, rmoar, Jason, shuah, linux-kselftest, kunit-dev, wireguard, netdev On Tue, 05 Mar 2024 10:37:06 PST (-0800), Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The ARCH_ and SOC_ versions of this symbol have persisted for quite a > while now in parallel. Generated .config files from previous LTS kernels > should have both. Finally remove SOC_VIRT and update all config files > using it. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > I had a 1.5 year old ack from Jason that I dropped due to the passage of > time. > > CC: Paul Walmsley <paul.walmsley@sifive.com> > CC: Palmer Dabbelt <palmer@dabbelt.com> > CC: Albert Ou <aou@eecs.berkeley.edu> > CC: Brendan Higgins <brendan.higgins@linux.dev> > CC: David Gow <davidgow@google.com> > CC: Rae Moar <rmoar@google.com> > CC: "Jason A. Donenfeld" <Jason@zx2c4.com> > CC: Shuah Khan <shuah@kernel.org> > CC: linux-riscv@lists.infradead.org > CC: linux-kernel@vger.kernel.org > CC: linux-kselftest@vger.kernel.org > CC: kunit-dev@googlegroups.com > CC: wireguard@lists.zx2c4.com > CC: netdev@vger.kernel.org > --- > arch/riscv/Kconfig.socs | 3 --- > arch/riscv/configs/defconfig | 2 +- > arch/riscv/configs/nommu_virt_defconfig | 2 +- > tools/testing/kunit/qemu_configs/riscv.py | 2 +- > tools/testing/selftests/wireguard/qemu/arch/riscv32.config | 2 +- > tools/testing/selftests/wireguard/qemu/arch/riscv64.config | 2 +- > 6 files changed, 5 insertions(+), 8 deletions(-) > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index e85ffb63c48d..dcbfb659839c 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -52,9 +52,6 @@ config ARCH_THEAD > This enables support for the RISC-V based T-HEAD SoCs. > > config ARCH_VIRT > - def_bool SOC_VIRT > - > -config SOC_VIRT > bool "QEMU Virt Machine" > select CLINT_TIMER if RISCV_M_MODE > select POWER_RESET > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig > index ab3bab313d56..8d46a9137b1e 100644 > --- a/arch/riscv/configs/defconfig > +++ b/arch/riscv/configs/defconfig > @@ -32,7 +32,7 @@ CONFIG_ARCH_SOPHGO=y > CONFIG_SOC_STARFIVE=y > CONFIG_ARCH_SUNXI=y > CONFIG_ARCH_THEAD=y > -CONFIG_SOC_VIRT=y > +CONFIG_ARCH_VIRT=y > CONFIG_SMP=y > CONFIG_HOTPLUG_CPU=y > CONFIG_PM=y > diff --git a/arch/riscv/configs/nommu_virt_defconfig b/arch/riscv/configs/nommu_virt_defconfig > index b794e2f8144e..de8143d1f738 100644 > --- a/arch/riscv/configs/nommu_virt_defconfig > +++ b/arch/riscv/configs/nommu_virt_defconfig > @@ -24,7 +24,7 @@ CONFIG_EXPERT=y > CONFIG_SLUB=y > CONFIG_SLUB_TINY=y > # CONFIG_MMU is not set > -CONFIG_SOC_VIRT=y > +CONFIG_ARCH_VIRT=y > CONFIG_NONPORTABLE=y > CONFIG_SMP=y > CONFIG_CMDLINE="root=/dev/vda rw earlycon=uart8250,mmio,0x10000000,115200n8 console=ttyS0" > diff --git a/tools/testing/kunit/qemu_configs/riscv.py b/tools/testing/kunit/qemu_configs/riscv.py > index 12a1d525978a..c87758030ff7 100644 > --- a/tools/testing/kunit/qemu_configs/riscv.py > +++ b/tools/testing/kunit/qemu_configs/riscv.py > @@ -13,7 +13,7 @@ if not os.path.isfile(OPENSBI_PATH): > > QEMU_ARCH = QemuArchParams(linux_arch='riscv', > kconfig=''' > -CONFIG_SOC_VIRT=y > +CONFIG_ARCH_VIRT=y > CONFIG_SERIAL_8250=y > CONFIG_SERIAL_8250_CONSOLE=y > CONFIG_SERIAL_OF_PLATFORM=y > diff --git a/tools/testing/selftests/wireguard/qemu/arch/riscv32.config b/tools/testing/selftests/wireguard/qemu/arch/riscv32.config > index 2fc36efb166d..2500eaa9b469 100644 > --- a/tools/testing/selftests/wireguard/qemu/arch/riscv32.config > +++ b/tools/testing/selftests/wireguard/qemu/arch/riscv32.config > @@ -2,7 +2,7 @@ CONFIG_NONPORTABLE=y > CONFIG_ARCH_RV32I=y > CONFIG_MMU=y > CONFIG_FPU=y > -CONFIG_SOC_VIRT=y > +CONFIG_ARCH_VIRT=y > CONFIG_SERIAL_8250=y > CONFIG_SERIAL_8250_CONSOLE=y > CONFIG_SERIAL_OF_PLATFORM=y > diff --git a/tools/testing/selftests/wireguard/qemu/arch/riscv64.config b/tools/testing/selftests/wireguard/qemu/arch/riscv64.config > index dc266f3b1915..29a67ac67766 100644 > --- a/tools/testing/selftests/wireguard/qemu/arch/riscv64.config > +++ b/tools/testing/selftests/wireguard/qemu/arch/riscv64.config > @@ -1,7 +1,7 @@ > CONFIG_ARCH_RV64I=y > CONFIG_MMU=y > CONFIG_FPU=y > -CONFIG_SOC_VIRT=y > +CONFIG_ARCH_VIRT=y > CONFIG_SERIAL_8250=y > CONFIG_SERIAL_8250_CONSOLE=y > CONFIG_SERIAL_OF_PLATFORM=y Acked-by: Palmer Dabbelt <palmer@rivosinc.com> _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1 1/2] RISC-V: drop SOC_SIFIVE for ARCH_SIFIVE 2024-03-05 18:37 [PATCH v1 1/2] RISC-V: drop SOC_SIFIVE for ARCH_SIFIVE Conor Dooley 2024-03-05 18:37 ` [PATCH v1 2/2] RISC-V: drop SOC_VIRT for ARCH_VIRT Conor Dooley @ 2024-03-12 4:34 ` Samuel Holland 2024-04-03 18:22 ` Palmer Dabbelt 2024-04-10 10:44 ` Conor Dooley 3 siblings, 0 replies; 6+ messages in thread From: Samuel Holland @ 2024-03-12 4:34 UTC (permalink / raw) To: Conor Dooley, linux-riscv Cc: Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-kernel On 2024-03-05 12:37 PM, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > All the users in the kernel are gone and generated .config files from > previous LTS kernels will contain ARCH_SIFIVE. Drop SOC_SIFIVE and > update the defconfig. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > CC: Paul Walmsley <paul.walmsley@sifive.com> > CC: Palmer Dabbelt <palmer@dabbelt.com> > CC: Albert Ou <aou@eecs.berkeley.edu> > CC: linux-riscv@lists.infradead.org > CC: linux-kernel@vger.kernel.org > --- > arch/riscv/Kconfig.socs | 3 --- > arch/riscv/configs/defconfig | 2 +- > 2 files changed, 1 insertion(+), 4 deletions(-) Reviewed-by: Samuel Holland <samuel.holland@sifive.com> _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1 1/2] RISC-V: drop SOC_SIFIVE for ARCH_SIFIVE 2024-03-05 18:37 [PATCH v1 1/2] RISC-V: drop SOC_SIFIVE for ARCH_SIFIVE Conor Dooley 2024-03-05 18:37 ` [PATCH v1 2/2] RISC-V: drop SOC_VIRT for ARCH_VIRT Conor Dooley 2024-03-12 4:34 ` [PATCH v1 1/2] RISC-V: drop SOC_SIFIVE for ARCH_SIFIVE Samuel Holland @ 2024-04-03 18:22 ` Palmer Dabbelt 2024-04-10 10:44 ` Conor Dooley 3 siblings, 0 replies; 6+ messages in thread From: Palmer Dabbelt @ 2024-04-03 18:22 UTC (permalink / raw) To: Conor Dooley Cc: linux-riscv, Conor Dooley, Conor Dooley, Paul Walmsley, aou, linux-kernel On Tue, 05 Mar 2024 10:37:05 PST (-0800), Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > All the users in the kernel are gone and generated .config files from > previous LTS kernels will contain ARCH_SIFIVE. Drop SOC_SIFIVE and > update the defconfig. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > CC: Paul Walmsley <paul.walmsley@sifive.com> > CC: Palmer Dabbelt <palmer@dabbelt.com> > CC: Albert Ou <aou@eecs.berkeley.edu> > CC: linux-riscv@lists.infradead.org > CC: linux-kernel@vger.kernel.org > --- > arch/riscv/Kconfig.socs | 3 --- > arch/riscv/configs/defconfig | 2 +- > 2 files changed, 1 insertion(+), 4 deletions(-) > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index e08e91c49abe..e85ffb63c48d 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -14,9 +14,6 @@ config ARCH_RENESAS > This enables support for the RISC-V based Renesas SoCs. > > config ARCH_SIFIVE > - def_bool SOC_SIFIVE > - > -config SOC_SIFIVE > bool "SiFive SoCs" > select ERRATA_SIFIVE if !XIP_KERNEL > help > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig > index 89a009a580fe..ab3bab313d56 100644 > --- a/arch/riscv/configs/defconfig > +++ b/arch/riscv/configs/defconfig > @@ -27,7 +27,7 @@ CONFIG_EXPERT=y > CONFIG_PROFILING=y > CONFIG_SOC_MICROCHIP_POLARFIRE=y > CONFIG_ARCH_RENESAS=y > -CONFIG_SOC_SIFIVE=y > +CONFIG_ARCH_SIFIVE=y > CONFIG_ARCH_SOPHGO=y > CONFIG_SOC_STARFIVE=y > CONFIG_ARCH_SUNXI=y Acked-by: Palmer Dabbelt <palmer@rivosinc.com> _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1 1/2] RISC-V: drop SOC_SIFIVE for ARCH_SIFIVE 2024-03-05 18:37 [PATCH v1 1/2] RISC-V: drop SOC_SIFIVE for ARCH_SIFIVE Conor Dooley ` (2 preceding siblings ...) 2024-04-03 18:22 ` Palmer Dabbelt @ 2024-04-10 10:44 ` Conor Dooley 3 siblings, 0 replies; 6+ messages in thread From: Conor Dooley @ 2024-04-10 10:44 UTC (permalink / raw) To: linux-riscv, Conor Dooley Cc: Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-kernel From: Conor Dooley <conor.dooley@microchip.com> On Tue, 05 Mar 2024 18:37:05 +0000, Conor Dooley wrote: > All the users in the kernel are gone and generated .config files from > previous LTS kernels will contain ARCH_SIFIVE. Drop SOC_SIFIVE and > update the defconfig. > > Applied to riscv-soc-for-next, thanks! [1/2] RISC-V: drop SOC_SIFIVE for ARCH_SIFIVE https://git.kernel.org/conor/c/d2a351e63779 [2/2] RISC-V: drop SOC_VIRT for ARCH_VIRT https://git.kernel.org/conor/c/1553a1c48281 Thanks, Conor. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2024-04-10 10:44 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-03-05 18:37 [PATCH v1 1/2] RISC-V: drop SOC_SIFIVE for ARCH_SIFIVE Conor Dooley 2024-03-05 18:37 ` [PATCH v1 2/2] RISC-V: drop SOC_VIRT for ARCH_VIRT Conor Dooley 2024-04-03 18:22 ` Palmer Dabbelt 2024-03-12 4:34 ` [PATCH v1 1/2] RISC-V: drop SOC_SIFIVE for ARCH_SIFIVE Samuel Holland 2024-04-03 18:22 ` Palmer Dabbelt 2024-04-10 10:44 ` Conor Dooley
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