From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB318C54E67 for ; Wed, 27 Mar 2024 12:10:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=5rRM1iIDM/frj/6FjJslN2niPDWNr52b2LwnHgjgjP0=; b=VX/XyaDJ2HEPeb 0Jph7nu5xL/KmNRwU+ucZu/UQWzCiqkJ9bUsxeasoJ4Onn6k24l8NwVdVcgZ4g+It5DzSYUpyLm3H ufom0mDbp9AxemXG0XMEDaEBYhYMjw4/+gKVy7JqQWTGm2RbO5AugC6q1ac1hGAbvrnyz3nlBkzh2 PqlG2OmXZ8hkgr155zR87t/ID/5Ug5l56F/OMBOvQEAJHLp/RDV76tT7DVsMGO0ckdYOyiyHtR1L1 tsgY9CxZPGngPDDdg1mDoXLmodmnodv6evFllD4iw8qlsG4hrqL2dC+bUcwSWVUdcsaekPywcLnCL CxHXkki/tZ65QPbNVaAQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rpS6h-00000008k67-1Cse; Wed, 27 Mar 2024 12:10:15 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rpS6d-00000008k39-3O8R for linux-riscv@lists.infradead.org; Wed, 27 Mar 2024 12:10:13 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 4FC7261507; Wed, 27 Mar 2024 12:10:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B159FC43390; Wed, 27 Mar 2024 12:10:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711541410; bh=CT9lboX6DGNHp4gMzO6XDm6vSdLnNJfbC/23vBoP+d8=; h=From:To:Cc:Subject:Date:From; b=qrDH+U6NpFvPXBwfEy0lyJQZJMlZCVEThnAP2wz1kh/nsprLQ7CLCOOUqVYmI3rMj RT4aMts5H1t+cmZUfqQE2lPvcMHwYewderAA5LLcuXkUHqJifMterLaFQWJfe4jPFl cPSyWjucgtAZoe60A3wEXBx9IzGjJYo1HniBESawCOA5Y/wgcZWomUJPaIWXgAIN7m v9nxoVXMret1FhlOhqtYUnHdCsB8bWQZmgfoGyzh57xABh5QzZm18cApr4fA7o+8sf Oa7ejQrPa4qb2XWdhJGDbnnqQSdWPEU95YvEIaoldjJk6cdjcUcZD/FGTTgaBjJLfh Zp2g5zogepU1Q== From: Sasha Levin To: stable@vger.kernel.org, leyfoon.tan@starfivetech.com Cc: Samuel Holland , Atish Patra , Daniel Lezcano , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: FAILED: Patch "clocksource/drivers/timer-riscv: Clear timer interrupt on timer initialization" failed to apply to 6.6-stable tree Date: Wed, 27 Mar 2024 08:10:08 -0400 Message-ID: <20240327121008.2827616-1-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Patchwork-Hint: ignore X-stable: review X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240327_051011_911394_A65E9874 X-CRM114-Status: GOOD ( 10.97 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The patch below does not apply to the 6.6-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . Thanks, Sasha ------------------ original commit in Linus's tree ------------------ >From 8248ca30ef89f9cc74ace62ae1b9a22b5f16736c Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Thu, 7 Mar 2024 01:23:30 +0800 Subject: [PATCH] clocksource/drivers/timer-riscv: Clear timer interrupt on timer initialization In the RISC-V specification, the stimecmp register doesn't have a default value. To prevent the timer interrupt from being triggered during timer initialization, clear the timer interrupt by writing stimecmp with a maximum value. Fixes: 9f7a8ff6391f ("RISC-V: Prefer sstc extension if available") Cc: Signed-off-by: Ley Foon Tan Reviewed-by: Samuel Holland Tested-by: Samuel Holland Reviewed-by: Atish Patra Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20240306172330.255844-1-leyfoon.tan@starfivetech.com --- drivers/clocksource/timer-riscv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index e66dcbd665665..79bb9a98baa7b 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -108,6 +108,9 @@ static int riscv_timer_starting_cpu(unsigned int cpu) { struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu); + /* Clear timer interrupt */ + riscv_clock_event_stop(); + ce->cpumask = cpumask_of(cpu); ce->irq = riscv_clock_event_irq; if (riscv_timer_cannot_wake_cpu) -- 2.43.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv