[PATCH 0/5] riscv: improve nommu and timer-clint

Jisheng Zhang
2024-03-25T16:53:45Z

As is known, the sophgo CV1800B contains so called little core, which
is C906 w/o MMU, so I want to run nommu linux on it. This series is
the result of the bring up. After this series, w/ proper dts, we can
run nommu linux on milkv duo's little core.

First of all, patch1 removes the PAGE_OFFSET hardcoding by introducing
DRAM_BASE Kconfig option.

The following patches try to improve the get_cycles and timer-clint
by always using TIME CSR, because Per the riscv privileged spec,
"The time CSR is a read-only shadow of the memory-mapped mtime
register", "On RV32I the timeh CSR is a read-only shadow of the upper
32 bits of the memory-mapped mtime register, while time shadows only
the lower 32 bits of mtime.".

The last patch adds T-Head C9xxx clint support to timer-clint driver.

Jisheng Zhang (5):
riscv: nommu: remove PAGE_OFFSET hardcoding
riscv: nommu: use CSR_TIME* for get_cycles* implementation
clocksource/drivers/timer-clint: Remove clint_time_val
clocksource/drivers/timer-clint: Use get_cycles()
clocksource/drivers/timer-clint: Add T-Head C9xx clint support

arch/riscv/Kconfig | 8 +++-
arch/riscv/include/asm/clint.h | 26 ------------
arch/riscv/include/asm/timex.h | 40 -------------------
drivers/clocksource/timer-clint.c | 66 ++++++++++++-------------------
4 files changed, 32 insertions(+), 108 deletions(-)
delete mode 100644 arch/riscv/include/asm/clint.h

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2.43.0