From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>,
Anup Patel <anup@brainfault.org>, Ajay Kaher <akaher@vmware.com>,
Alexandre Ghiti <alexghiti@rivosinc.com>,
Alexey Makhalov <amakhalov@vmware.com>,
Andrew Jones <ajones@ventanamicro.com>,
Conor Dooley <conor.dooley@microchip.com>,
Juergen Gross <jgross@suse.com>,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org,
Mark Rutland <mark.rutland@arm.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Shuah Khan <shuah@kernel.org>,
virtualization@lists.linux.dev,
VMware PV-Drivers Reviewers <pv-drivers@vmware.com>,
Will Deacon <will@kernel.org>,
x86@kernel.org
Subject: [PATCH v5 19/22] KVM: riscv: selftests: Add SBI PMU extension definitions
Date: Wed, 3 Apr 2024 01:04:48 -0700 [thread overview]
Message-ID: <20240403080452.1007601-20-atishp@rivosinc.com> (raw)
In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com>
The SBI PMU extension definition is required for upcoming SBI PMU
selftests.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
.../testing/selftests/kvm/include/riscv/sbi.h | 66 +++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/tools/testing/selftests/kvm/include/riscv/sbi.h b/tools/testing/selftests/kvm/include/riscv/sbi.h
index ba04f2dec7b5..6675ca673c77 100644
--- a/tools/testing/selftests/kvm/include/riscv/sbi.h
+++ b/tools/testing/selftests/kvm/include/riscv/sbi.h
@@ -29,17 +29,83 @@
enum sbi_ext_id {
SBI_EXT_BASE = 0x10,
SBI_EXT_STA = 0x535441,
+ SBI_EXT_PMU = 0x504D55,
};
enum sbi_ext_base_fid {
SBI_EXT_BASE_PROBE_EXT = 3,
};
+enum sbi_ext_pmu_fid {
+ SBI_EXT_PMU_NUM_COUNTERS = 0,
+ SBI_EXT_PMU_COUNTER_GET_INFO,
+ SBI_EXT_PMU_COUNTER_CFG_MATCH,
+ SBI_EXT_PMU_COUNTER_START,
+ SBI_EXT_PMU_COUNTER_STOP,
+ SBI_EXT_PMU_COUNTER_FW_READ,
+ SBI_EXT_PMU_COUNTER_FW_READ_HI,
+ SBI_EXT_PMU_SNAPSHOT_SET_SHMEM,
+};
+
+union sbi_pmu_ctr_info {
+ unsigned long value;
+ struct {
+ unsigned long csr:12;
+ unsigned long width:6;
+#if __riscv_xlen == 32
+ unsigned long reserved:13;
+#else
+ unsigned long reserved:45;
+#endif
+ unsigned long type:1;
+ };
+};
struct sbiret {
long error;
long value;
};
+/** General pmu event codes specified in SBI PMU extension */
+enum sbi_pmu_hw_generic_events_t {
+ SBI_PMU_HW_NO_EVENT = 0,
+ SBI_PMU_HW_CPU_CYCLES = 1,
+ SBI_PMU_HW_INSTRUCTIONS = 2,
+ SBI_PMU_HW_CACHE_REFERENCES = 3,
+ SBI_PMU_HW_CACHE_MISSES = 4,
+ SBI_PMU_HW_BRANCH_INSTRUCTIONS = 5,
+ SBI_PMU_HW_BRANCH_MISSES = 6,
+ SBI_PMU_HW_BUS_CYCLES = 7,
+ SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8,
+ SBI_PMU_HW_STALLED_CYCLES_BACKEND = 9,
+ SBI_PMU_HW_REF_CPU_CYCLES = 10,
+
+ SBI_PMU_HW_GENERAL_MAX,
+};
+
+/* SBI PMU counter types */
+enum sbi_pmu_ctr_type {
+ SBI_PMU_CTR_TYPE_HW = 0x0,
+ SBI_PMU_CTR_TYPE_FW,
+};
+
+/* Flags defined for config matching function */
+#define SBI_PMU_CFG_FLAG_SKIP_MATCH BIT(0)
+#define SBI_PMU_CFG_FLAG_CLEAR_VALUE BIT(1)
+#define SBI_PMU_CFG_FLAG_AUTO_START BIT(2)
+#define SBI_PMU_CFG_FLAG_SET_VUINH BIT(3)
+#define SBI_PMU_CFG_FLAG_SET_VSINH BIT(4)
+#define SBI_PMU_CFG_FLAG_SET_UINH BIT(5)
+#define SBI_PMU_CFG_FLAG_SET_SINH BIT(6)
+#define SBI_PMU_CFG_FLAG_SET_MINH BIT(7)
+
+/* Flags defined for counter start function */
+#define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0)
+#define SBI_PMU_START_FLAG_INIT_SNAPSHOT BIT(1)
+
+/* Flags defined for counter stop function */
+#define SBI_PMU_STOP_FLAG_RESET BIT(0)
+#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1)
+
struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
unsigned long arg1, unsigned long arg2,
unsigned long arg3, unsigned long arg4,
--
2.34.1
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next prev parent reply other threads:[~2024-04-03 8:06 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-03 8:04 [PATCH v5 00/22] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest Atish Patra
2024-04-03 8:04 ` [PATCH v5 01/22] RISC-V: Fix the typo in Scountovf CSR name Atish Patra
2024-04-04 10:56 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 02/22] RISC-V: Add FIRMWARE_READ_HI definition Atish Patra
2024-04-04 10:57 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 03/22] drivers/perf: riscv: Read upper bits of a firmware counter Atish Patra
2024-04-04 11:02 ` Andrew Jones
2024-04-09 0:04 ` Atish Patra
2024-04-03 8:04 ` [PATCH v5 04/22] drivers/perf: riscv: Use BIT macro for shifting operations Atish Patra
2024-04-04 11:08 ` Andrew Jones
2024-04-09 0:20 ` Atish Patra
2024-04-03 8:04 ` [PATCH v5 05/22] RISC-V: Add SBI PMU snapshot definitions Atish Patra
2024-04-04 11:14 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 06/22] drivers/perf: riscv: Implement SBI PMU snapshot function Atish Patra
2024-04-04 11:52 ` Andrew Jones
2024-04-10 22:29 ` Atish Patra
2024-04-11 7:45 ` Andrew Jones
2024-04-04 12:01 ` Andrew Jones
2024-04-09 0:21 ` Atish Patra
2024-04-03 8:04 ` [PATCH v5 07/22] drivers/perf: riscv: Fix counter mask iteration for RV32 Atish Patra
2024-04-04 11:55 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 08/22] RISC-V: KVM: Fix the initial sample period value Atish Patra
2024-04-04 11:57 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 09/22] RISC-V: KVM: Rename the SBI_STA_SHMEM_DISABLE to a generic name Atish Patra
2024-04-04 11:59 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 10/22] RISC-V: KVM: No need to update the counter value during reset Atish Patra
2024-04-03 8:04 ` [PATCH v5 11/22] RISC-V: KVM: No need to exit to the user space if perf event failed Atish Patra
2024-04-04 12:19 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 12/22] RISC-V: KVM: Implement SBI PMU Snapshot feature Atish Patra
2024-04-05 11:23 ` Andrew Jones
2024-04-09 0:33 ` Atish Patra
2024-04-03 8:04 ` [PATCH v5 13/22] RISC-V: KVM: Add perf sampling support for guests Atish Patra
2024-04-05 11:36 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 14/22] RISC-V: KVM: Support 64 bit firmware counters on RV32 Atish Patra
2024-04-05 12:10 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 15/22] RISC-V: KVM: Improve firmware counter read function Atish Patra
2024-04-05 12:12 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 16/22] KVM: riscv: selftests: Move sbi definitions to its own header file Atish Patra
2024-04-05 12:16 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 17/22] KVM: riscv: selftests: Add helper functions for extension checks Atish Patra
2024-04-05 12:17 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 18/22] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test Atish Patra
2024-04-03 8:04 ` Atish Patra [this message]
2024-04-05 12:20 ` [PATCH v5 19/22] KVM: riscv: selftests: Add SBI PMU extension definitions Andrew Jones
2024-04-03 8:04 ` [PATCH v5 20/22] KVM: riscv: selftests: Add SBI PMU selftest Atish Patra
2024-04-05 12:50 ` Andrew Jones
2024-04-09 0:37 ` Atish Patra
2024-04-09 8:01 ` Andrew Jones
2024-04-09 22:11 ` Atish Kumar Patra
2024-04-03 8:04 ` [PATCH v5 21/22] KVM: riscv: selftests: Add a test for PMU snapshot functionality Atish Patra
2024-04-05 13:11 ` Andrew Jones
2024-04-09 22:52 ` Atish Patra
2024-04-10 7:10 ` Andrew Jones
2024-04-10 7:28 ` Atish Patra
2024-04-10 7:54 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 22/22] KVM: riscv: selftests: Add a test for counter overflow Atish Patra
2024-04-05 13:23 ` Andrew Jones
2024-04-09 23:47 ` Atish Patra
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