From: Conor Dooley <conor@kernel.org>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: Samuel Holland <samuel.holland@sifive.com>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Eric Lin <eric.lin@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v1 0/6] SiFive cache controller PMU drivers
Date: Tue, 9 Apr 2024 16:01:15 +0100 [thread overview]
Message-ID: <20240409-corral-untruth-591b29f6565d@spud> (raw)
In-Reply-To: <20240216-shopping-unnoticed-e73e72a0e849@wendy>
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On Fri, Feb 16, 2024 at 10:05:04AM +0000, Conor Dooley wrote:
> On Thu, Feb 15, 2024 at 04:08:12PM -0800, Samuel Holland wrote:
>
> > All three of these cache controllers (with PMUs) have been integrated in
> > SoCs by our customers. However, as none of those SoCs have been publicly
> > announced yet, I cannot include SoC-specific compatible strings in this
> > version of the devicetree bindings.
>
> And I don't want to apply any of those dt-binding patches until then.
> Stuff like "sifive,perfmon-counters" seems like a property that would
> go away with a device-specific compatible, at least for the ccache.
Reading the P550 stuff today reminded me that I had not got around to
looking at this series again. You should be able to use that to satisfy
my wish for some soc-specific compatibles, right?
And w.r.r. the perfmon-counters property, looked to me like Rob was
proposing it not even having to be vendor specific.
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prev parent reply other threads:[~2024-04-09 15:01 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-16 0:08 [PATCH v1 0/6] SiFive cache controller PMU drivers Samuel Holland
2024-02-16 0:08 ` [PATCH v1 1/6] dt-bindings: cache: Document the sifive,perfmon-counters property Samuel Holland
2024-02-17 9:00 ` Krzysztof Kozlowski
2024-02-18 15:29 ` Samuel Holland
2024-02-18 18:35 ` Krzysztof Kozlowski
2024-02-22 19:36 ` Rob Herring
2024-04-09 15:03 ` Conor Dooley
2024-02-16 0:08 ` [PATCH v1 2/6] drivers/perf: Add SiFive Composable Cache PMU driver Samuel Holland
2024-02-19 11:29 ` Jonathan Cameron
2024-04-11 11:05 ` Robin Murphy
2024-02-16 0:08 ` [PATCH v1 3/6] dt-bindings: cache: Add SiFive Extensible Cache controller Samuel Holland
2024-02-17 9:09 ` Krzysztof Kozlowski
2024-02-18 15:50 ` Samuel Holland
2024-02-16 0:08 ` [PATCH v1 4/6] drivers/perf: Add SiFive Extensible Cache PMU driver Samuel Holland
2024-02-19 11:40 ` Jonathan Cameron
2024-02-16 0:08 ` [PATCH v1 5/6] dt-bindings: cache: Add SiFive Private L2 Cache controller Samuel Holland
2024-02-17 9:12 ` Krzysztof Kozlowski
2024-02-18 15:33 ` Samuel Holland
2024-02-16 0:08 ` [PATCH v1 6/6] drivers/perf: Add SiFive Private L2 Cache PMU driver Samuel Holland
2024-02-16 10:05 ` [PATCH v1 0/6] SiFive cache controller PMU drivers Conor Dooley
2024-04-09 15:01 ` Conor Dooley [this message]
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