Re: [PATCH v2 7/7] iommu/riscv: Paging domain support

Baolu Lu
2024-04-22T07:41:14Z

On 2024/4/19 20:56, Jason Gunthorpe wrote:
>> + riscv_iommu_cmd_inval_vma(&cmd);
>> + riscv_iommu_cmd_inval_set_pscid(&cmd, domain->pscid);
>> + if (len > 0 && len < RISCV_IOMMU_IOTLB_INVAL_LIMIT) {
>> + for (iova = start; iova < end; iova += PAGE_SIZE) {
>> + riscv_iommu_cmd_inval_set_addr(&cmd, iova);
>> + riscv_iommu_cmd_send(iommu, &cmd, 0);
>> + }
>> + } else {
>> + riscv_iommu_cmd_send(iommu, &cmd, 0);
>> + }
>> + }
> This seems suboptimal, you probably want to copy the new design that
> Intel is doing where you allocate "bonds" that are already
> de-duplicated. Ie if I have 10 devices on the same iommu sharing the
> domain the above will invalidate the PSCID 10 times. It should only be
> done once.
>
> ie add a "bond" for the (iommu,pscid) and refcount that based on how
> many devices are used. Then another "bond" for the ATS stuff eventually.

The latest version is under discussion here.

https://lore.kernel.org/linux-iommu/20240416080656.60968-1-baolu.lu@linux.intel.com/

Supposedly, you can make such optimization after the base code is landed
in the mainline tree if the change is big.

Best regards,
baolu