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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 17-20020a170906311100b00a5599f3a057sm7714032ejx.107.2024.04.26.02.02.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 02:02:36 -0700 (PDT) Date: Fri, 26 Apr 2024 11:02:30 +0200 From: Andrew Jones To: Charlie Jenkins Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Conor Dooley , Conor Dooley , =?utf-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= , Evan Green , Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] riscv: cpufeature: Fix thead vector hwcap removal Message-ID: <20240426-d8aba0211e882568ccc761df@orel> References: <20240424-cpufeature_fixes-v1-0-585e73d2226b@rivosinc.com> <20240424-cpufeature_fixes-v1-1-585e73d2226b@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240424-cpufeature_fixes-v1-1-585e73d2226b@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240426_020240_241299_0A90EFD5 X-CRM114-Status: GOOD ( 14.35 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Apr 24, 2024 at 09:19:54AM GMT, Charlie Jenkins wrote: ... > + /* > + * Naively assume that all harts have the same mvendorid/marchid as the > + * boot hart. This comment isn't necessary, since we don't have to assume all harts have the same IDs. This information is currently being collected specifically for thead. So, we can state in a comment below, where the information is used, that we assume when the boot hart is thead, then we don't want to enable V on any hart (whatever their IDs are). Thanks, drew > + */ > + boot_vendorid = riscv_get_mvendorid(); > + boot_archid = riscv_get_marchid(); > + > for_each_possible_cpu(cpu) { > struct riscv_isainfo *isainfo = &hart_isa[cpu]; > unsigned long this_hwcap = 0; > @@ -544,8 +553,7 @@ static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) > * CPU cores with the ratified spec will contain non-zero > * marchid. > */ > - if (acpi_disabled && riscv_cached_mvendorid(cpu) == THEAD_VENDOR_ID && > - riscv_cached_marchid(cpu) == 0x0) { > + if (acpi_disabled && boot_vendorid == THEAD_VENDOR_ID && boot_archid == 0x0) { > this_hwcap &= ~isa2hwcap[RISCV_ISA_EXT_v]; > clear_bit(RISCV_ISA_EXT_v, isainfo->isa); > } > > -- > 2.44.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv