From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Cc: aou@eecs.berkeley.edu, jeeheng.sia@starfivetech.com,
rafael.j.wysocki@intel.com, conor.dooley@microchip.com,
palmer@dabbelt.com, paul.walmsley@sifive.com,
ajones@ventanamicro.com
Subject: [PATCH v2 0/1] Enable SPCR table for console output on RISC-V
Date: Thu, 2 May 2024 00:37:50 -0700 [thread overview]
Message-ID: <20240502073751.102093-1-jeeheng.sia@starfivetech.com> (raw)
The ACPI SPCR code has been used to enable console output for ARM64 and
X86. The same code can be reused for RISC-V. Furthermore, SPCR table is
mandated for headless system as outlined in the RISC-V BRS
Specification, chapter 6.
Changes in v2:
- Added code to handle early_init_dt_scan_chosen_stdout().
Sia Jee Heng (1):
RISC-V: ACPI: Enable SPCR table for console output on RISC-V
arch/riscv/Kconfig | 1 +
arch/riscv/kernel/acpi.c | 12 +++++++++++-
2 files changed, 12 insertions(+), 1 deletion(-)
base-commit: 0106679839f7c69632b3b9833c3268c316c0a9fc
--
2.34.1
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next reply other threads:[~2024-05-02 7:38 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-02 7:37 Sia Jee Heng [this message]
2024-05-02 7:37 ` [PATCH v2 1/1] RISC-V: ACPI: Enable SPCR table for console output on RISC-V Sia Jee Heng
2024-07-09 4:49 ` Sunil V L
2024-07-25 13:20 ` [PATCH v2 0/1] " patchwork-bot+linux-riscv
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