Re: [PATCH v3 1/2] dt-bindings: phy: Add Sophgo CV1800 USB phy

Krzysztof Kozlowski
2024-05-06T06:52:21Z

On 05/05/2024 03:52, Inochi Amaoto wrote:
> The USB phy of Sophgo CV18XX series SoC needs to sense a pin called
> "VBUS_DET" to get the right operation mode. If this pin is not
> connected, it only supports setting the mode manually.
>
> Add USB phy bindings for Sophgo CV18XX/SG200X series SoC.

...

> +
> + clock-names:
> + items:
> + - const: phy
> + - const: app
> + - const: stb
> + - const: lpm
> +
> + vbus_det-gpios:

No underscores.

> + description: GPIO to the USB OTG VBUS detect pin. This should not be
> + defined if vbus_det pin and switch pin are connected, which may
> + break the VBUS detection.

Why is this property of the PHY? VBUS pin goes to the connector, doesn't
it? It looks like you combined two or three (!!!) bindings into one.

> + maxItems: 1
> +
> + sophgo,switch-gpios:
> + description: GPIO array for the phy to control connected switch. For

Switch? This is a binding of the phy, not switch...

> + host mode, the driver will set these GPIOs to low one by one. For

Yeah, you mention driver which further confirms this is a property for
driver, not hardware.

Describe your hardware, not driver behavior.

> + device mode, the driver will set these GPIOs to high in reverse
> + order. For a reference design, see item description.
> + minItems: 1
> + items:
> + - description: USB switch operation mode
> + - description: USB switch host power control
> +
> +required:
> + - compatible
> + - "#phy-cells"
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + phy@48 {
> + compatible = "sophgo,cv1800-usb-phy";
> + reg = <0x48 0x4>;
> + #phy-cells = <0>;
> + clocks = <&clk 92>, <&clk 93>,
> + <&clk 94>, <&clk 95>;
> + clock-names = "phy", "app", "stb", "lpm";

Make the example complete.

Best regards,
Krzysztof