[PATCH] riscv, bpf: Optimize zextw insn with Zba extension

[PATCH] riscv, bpf: Optimize zextw insn with Zba extension

[Xiao Wang]

The Zba extension provides add.uw insn which can be used to implement
zext.w with rs2 set as ZERO.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
---
 arch/riscv/Kconfig       | 19 +++++++++++++++++++
 arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++
 2 files changed, 37 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6bec1bce6586..0679127cc0ea 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -586,6 +586,14 @@ config RISCV_ISA_V_PREEMPTIVE
 	  preemption. Enabling this config will result in higher memory
 	  consumption due to the allocation of per-task's kernel Vector context.
 
+config TOOLCHAIN_HAS_ZBA
+	bool
+	default y
+	depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
+	depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
+	depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
+	depends on AS_HAS_OPTION_ARCH
+
 config TOOLCHAIN_HAS_ZBB
 	bool
 	default y
@@ -601,6 +609,17 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO
 	def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb)
 	depends on AS_HAS_OPTION_ARCH
 
+config RISCV_ISA_ZBA
+	bool "Zba extension support for bit manipulation instructions"
+	depends on TOOLCHAIN_HAS_ZBA
+	depends on RISCV_ALTERNATIVE
+	default y
+	help
+	   Adds support to dynamically detect the presence of the ZBA
+	   extension (address generation acceleration) and enable its usage.
+
+	   If you don't know what to do here, say Y.
+
 config RISCV_ISA_ZBB
 	bool "Zbb extension support for bit manipulation instructions"
 	depends on TOOLCHAIN_HAS_ZBB
diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h
index f4b6b3b9edda..18a7885ba95e 100644
--- a/arch/riscv/net/bpf_jit.h
+++ b/arch/riscv/net/bpf_jit.h
@@ -18,6 +18,11 @@ static inline bool rvc_enabled(void)
 	return IS_ENABLED(CONFIG_RISCV_ISA_C);
 }
 
+static inline bool rvzba_enabled(void)
+{
+	return IS_ENABLED(CONFIG_RISCV_ISA_ZBA) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBA);
+}
+
 static inline bool rvzbb_enabled(void)
 {
 	return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB);
@@ -937,6 +942,14 @@ static inline u16 rvc_sdsp(u32 imm9, u8 rs2)
 	return rv_css_insn(0x7, imm, rs2, 0x2);
 }
 
+/* RV64-only ZBA instructions. */
+
+static inline u32 rvzba_zextw(u8 rd, u8 rs1)
+{
+	/* add.uw rd, rs1, ZERO */
+	return rv_r_insn(0x04, RV_REG_ZERO, rs1, 0, rd, 0x3b);
+}
+
 #endif /* __riscv_xlen == 64 */
 
 /* Helper functions that emit RVC instructions when possible. */
@@ -1159,6 +1172,11 @@ static inline void emit_zexth(u8 rd, u8 rs, struct rv_jit_context *ctx)
 
 static inline void emit_zextw(u8 rd, u8 rs, struct rv_jit_context *ctx)
 {
+	if (rvzba_enabled()) {
+		emit(rvzba_zextw(rd, rs), ctx);
+		return;
+	}
+
 	emit_slli(rd, rs, 32, ctx);
 	emit_srli(rd, rd, 32, ctx);
 }
-- 
2.25.1


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Re: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension

[Pu Lehui]

On 2024/5/7 18:45, Xiao Wang wrote:
> The Zba extension provides add.uw insn which can be used to implement
> zext.w with rs2 set as ZERO.
> 
> Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
> ---
>   arch/riscv/Kconfig       | 19 +++++++++++++++++++
>   arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++
>   2 files changed, 37 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 6bec1bce6586..0679127cc0ea 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -586,6 +586,14 @@ config RISCV_ISA_V_PREEMPTIVE
>   	  preemption. Enabling this config will result in higher memory
>   	  consumption due to the allocation of per-task's kernel Vector context.
>   
> +config TOOLCHAIN_HAS_ZBA
> +	bool
> +	default y
> +	depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
> +	depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
> +	depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
> +	depends on AS_HAS_OPTION_ARCH
> +
>   config TOOLCHAIN_HAS_ZBB
>   	bool
>   	default y
> @@ -601,6 +609,17 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO
>   	def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb)
>   	depends on AS_HAS_OPTION_ARCH
>   
> +config RISCV_ISA_ZBA
> +	bool "Zba extension support for bit manipulation instructions"
> +	depends on TOOLCHAIN_HAS_ZBA
> +	depends on RISCV_ALTERNATIVE
> +	default y
> +	help
> +	   Adds support to dynamically detect the presence of the ZBA
> +	   extension (address generation acceleration) and enable its usage.

It would be better to add Zba's function description like Zbb.

> +
> +	   If you don't know what to do here, say Y.
> +
>   config RISCV_ISA_ZBB
>   	bool "Zbb extension support for bit manipulation instructions"
>   	depends on TOOLCHAIN_HAS_ZBB
> diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h
> index f4b6b3b9edda..18a7885ba95e 100644
> --- a/arch/riscv/net/bpf_jit.h
> +++ b/arch/riscv/net/bpf_jit.h
> @@ -18,6 +18,11 @@ static inline bool rvc_enabled(void)
>   	return IS_ENABLED(CONFIG_RISCV_ISA_C);
>   }
>   
> +static inline bool rvzba_enabled(void)
> +{
> +	return IS_ENABLED(CONFIG_RISCV_ISA_ZBA) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBA);
> +}
> +
>   static inline bool rvzbb_enabled(void)
>   {
>   	return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB);
> @@ -937,6 +942,14 @@ static inline u16 rvc_sdsp(u32 imm9, u8 rs2)
>   	return rv_css_insn(0x7, imm, rs2, 0x2);
>   }
>   
> +/* RV64-only ZBA instructions. */
> +
> +static inline u32 rvzba_zextw(u8 rd, u8 rs1)
> +{
> +	/* add.uw rd, rs1, ZERO */
> +	return rv_r_insn(0x04, RV_REG_ZERO, rs1, 0, rd, 0x3b);
> +}
> +
>   #endif /* __riscv_xlen == 64 */
>   
>   /* Helper functions that emit RVC instructions when possible. */
> @@ -1159,6 +1172,11 @@ static inline void emit_zexth(u8 rd, u8 rs, struct rv_jit_context *ctx)
>   
>   static inline void emit_zextw(u8 rd, u8 rs, struct rv_jit_context *ctx)
>   {
> +	if (rvzba_enabled()) {
> +		emit(rvzba_zextw(rd, rs), ctx);
> +		return;
> +	}

Looks good to me. It seems that Zba has fewer uses in rv64 bpf jit.

> +
>   	emit_slli(rd, rs, 32, ctx);
>   	emit_srli(rd, rd, 32, ctx);
>   }

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Re: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension

[Ben Dooks]

On 07/05/2024 13:47, Pu Lehui wrote:
> 
> On 2024/5/7 18:45, Xiao Wang wrote:
>> The Zba extension provides add.uw insn which can be used to implement
>> zext.w with rs2 set as ZERO.
>>
>> Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
>> ---
>>   arch/riscv/Kconfig       | 19 +++++++++++++++++++
>>   arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++
>>   2 files changed, 37 insertions(+)
>>
>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> index 6bec1bce6586..0679127cc0ea 100644
>> --- a/arch/riscv/Kconfig
>> +++ b/arch/riscv/Kconfig
>> @@ -586,6 +586,14 @@ config RISCV_ISA_V_PREEMPTIVE
>>         preemption. Enabling this config will result in higher memory
>>         consumption due to the allocation of per-task's kernel Vector 
>> context.
>> +config TOOLCHAIN_HAS_ZBA
>> +    bool
>> +    default y
>> +    depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
>> +    depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
>> +    depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
>> +    depends on AS_HAS_OPTION_ARCH
>> +
>>   config TOOLCHAIN_HAS_ZBB

At this point would it be easier to ask the toolchain what's enabled
and put into kconfig via some sort of script?

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html


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RE: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension

[Wang, Xiao W]

Hi Ben,

> -----Original Message-----
> From: ben.dooks@codethink.co.uk <ben.dooks@codethink.co.uk>
> Sent: Tuesday, May 7, 2024 10:00 PM
> To: Pu Lehui <pulehui@huawei.com>; Wang, Xiao W
> <xiao.w.wang@intel.com>; paul.walmsley@sifive.com; palmer@dabbelt.com;
> aou@eecs.berkeley.edu; luke.r.nels@gmail.com; xi.wang@gmail.com;
> bjorn@kernel.org
> Cc: ast@kernel.org; daniel@iogearbox.net; andrii@kernel.org;
> martin.lau@linux.dev; eddyz87@gmail.com; song@kernel.org;
> yonghong.song@linux.dev; john.fastabend@gmail.com; kpsingh@kernel.org;
> sdf@google.com; haoluo@google.com; jolsa@kernel.org; linux-
> riscv@lists.infradead.org; linux-kernel@vger.kernel.org; bpf@vger.kernel.org;
> Li, Haicheng <haicheng.li@intel.com>
> Subject: Re: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension
> 
> On 07/05/2024 13:47, Pu Lehui wrote:
> >
> > On 2024/5/7 18:45, Xiao Wang wrote:
> >> The Zba extension provides add.uw insn which can be used to implement
> >> zext.w with rs2 set as ZERO.
> >>
> >> Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
> >> ---
> >>   arch/riscv/Kconfig       | 19 +++++++++++++++++++
> >>   arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++
> >>   2 files changed, 37 insertions(+)
> >>
> >> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> >> index 6bec1bce6586..0679127cc0ea 100644
> >> --- a/arch/riscv/Kconfig
> >> +++ b/arch/riscv/Kconfig
> >> @@ -586,6 +586,14 @@ config RISCV_ISA_V_PREEMPTIVE
> >>         preemption. Enabling this config will result in higher memory
> >>         consumption due to the allocation of per-task's kernel Vector
> >> context.
> >> +config TOOLCHAIN_HAS_ZBA
> >> +    bool
> >> +    default y
> >> +    depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
> >> +    depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
> >> +    depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
> >> +    depends on AS_HAS_OPTION_ARCH
> >> +
> >>   config TOOLCHAIN_HAS_ZBB
> 
> At this point would it be easier to ask the toolchain what's enabled
> and put into kconfig via some sort of script?

You mean to use some sort of script to automatically detect whether LD linker
can support a certain riscv extension?

I just went through the help guide of riscv64-linux-gnu-ld, and did some trial,
the "--architecture" argument usage is different from the CC's "-march". I can't find
other relevant args. It looks currently there's no direct method to dump the
supported riscv extensions of a LD.

Then I tried below test to see if we can check it via building from /dev/null, just like
the cc-option does.
Note: here CC is Zbb capable
CC -march=rv64gc_zbb -x c -c /dev/null -o tmp.o && LD tmp.o -o tmp.elf

I find that whether LD is Zbb capable or not, the above command just outputs
"warning: cannot find entry symbol _start ..", no error comes with older LD.
When we provide some Zbb-arch-tagged non-empty *.o file to the LD, then 
the older LD would error out "unsupported ISA subset ..".
But I'm afraid it's not a good idea to add a source file for each extension detection.

Maybe in future there would be an easy way to ask the LD what riscv extensions
are supported.

BRs,
Xiao

> 
> --
> Ben Dooks				http://www.codethink.co.uk/
> Senior Engineer				Codethink - Providing Genius
> 
> https://www.codethink.co.uk/privacy.html

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RE: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension

[Wang, Xiao W]

> -----Original Message-----
> From: Pu Lehui <pulehui@huawei.com>
> Sent: Tuesday, May 7, 2024 8:47 PM
> To: Wang, Xiao W <xiao.w.wang@intel.com>; paul.walmsley@sifive.com;
> palmer@dabbelt.com; aou@eecs.berkeley.edu; luke.r.nels@gmail.com;
> xi.wang@gmail.com; bjorn@kernel.org
> Cc: ast@kernel.org; daniel@iogearbox.net; andrii@kernel.org;
> martin.lau@linux.dev; eddyz87@gmail.com; song@kernel.org;
> yonghong.song@linux.dev; john.fastabend@gmail.com; kpsingh@kernel.org;
> sdf@google.com; haoluo@google.com; jolsa@kernel.org; linux-
> riscv@lists.infradead.org; linux-kernel@vger.kernel.org; bpf@vger.kernel.org;
> Li, Haicheng <haicheng.li@intel.com>
> Subject: Re: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension
> 
> 
> On 2024/5/7 18:45, Xiao Wang wrote:
> > The Zba extension provides add.uw insn which can be used to implement
> > zext.w with rs2 set as ZERO.
> >
> > Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
> > ---
> >   arch/riscv/Kconfig       | 19 +++++++++++++++++++
> >   arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++
> >   2 files changed, 37 insertions(+)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 6bec1bce6586..0679127cc0ea 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -586,6 +586,14 @@ config RISCV_ISA_V_PREEMPTIVE
> >   	  preemption. Enabling this config will result in higher memory
> >   	  consumption due to the allocation of per-task's kernel Vector
> context.
> >
> > +config TOOLCHAIN_HAS_ZBA
> > +	bool
> > +	default y
> > +	depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
> > +	depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
> > +	depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
> > +	depends on AS_HAS_OPTION_ARCH
> > +
> >   config TOOLCHAIN_HAS_ZBB
> >   	bool
> >   	default y
> > @@ -601,6 +609,17 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO
> >   	def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb)
> >   	depends on AS_HAS_OPTION_ARCH
> >
> > +config RISCV_ISA_ZBA
> > +	bool "Zba extension support for bit manipulation instructions"
> > +	depends on TOOLCHAIN_HAS_ZBA
> > +	depends on RISCV_ALTERNATIVE
> > +	default y
> > +	help
> > +	   Adds support to dynamically detect the presence of the ZBA
> > +	   extension (address generation acceleration) and enable its usage.
> 
> It would be better to add Zba's function description like Zbb.

OK, would add some description on next version.

Thanks,
Xiao

> 
> > +
> > +	   If you don't know what to do here, say Y.
> > +
> >   config RISCV_ISA_ZBB
> >   	bool "Zbb extension support for bit manipulation instructions"
> >   	depends on TOOLCHAIN_HAS_ZBB
> > diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h
> > index f4b6b3b9edda..18a7885ba95e 100644
> > --- a/arch/riscv/net/bpf_jit.h
> > +++ b/arch/riscv/net/bpf_jit.h
> > @@ -18,6 +18,11 @@ static inline bool rvc_enabled(void)
> >   	return IS_ENABLED(CONFIG_RISCV_ISA_C);
> >   }
> >
> > +static inline bool rvzba_enabled(void)
> > +{
> > +	return IS_ENABLED(CONFIG_RISCV_ISA_ZBA) &&
> riscv_has_extension_likely(RISCV_ISA_EXT_ZBA);
> > +}
> > +
> >   static inline bool rvzbb_enabled(void)
> >   {
> >   	return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&
> riscv_has_extension_likely(RISCV_ISA_EXT_ZBB);
> > @@ -937,6 +942,14 @@ static inline u16 rvc_sdsp(u32 imm9, u8 rs2)
> >   	return rv_css_insn(0x7, imm, rs2, 0x2);
> >   }
> >
> > +/* RV64-only ZBA instructions. */
> > +
> > +static inline u32 rvzba_zextw(u8 rd, u8 rs1)
> > +{
> > +	/* add.uw rd, rs1, ZERO */
> > +	return rv_r_insn(0x04, RV_REG_ZERO, rs1, 0, rd, 0x3b);
> > +}
> > +
> >   #endif /* __riscv_xlen == 64 */
> >
> >   /* Helper functions that emit RVC instructions when possible. */
> > @@ -1159,6 +1172,11 @@ static inline void emit_zexth(u8 rd, u8 rs, struct
> rv_jit_context *ctx)
> >
> >   static inline void emit_zextw(u8 rd, u8 rs, struct rv_jit_context *ctx)
> >   {
> > +	if (rvzba_enabled()) {
> > +		emit(rvzba_zextw(rd, rs), ctx);
> > +		return;
> > +	}
> 
> Looks good to me. It seems that Zba has fewer uses in rv64 bpf jit.
> 
> > +
> >   	emit_slli(rd, rs, 32, ctx);
> >   	emit_srli(rd, rd, 32, ctx);
> >   }
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Re: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 2035 bytes --]

On Tue, May 07, 2024 at 06:45:28PM +0800, Xiao Wang wrote:
> The Zba extension provides add.uw insn which can be used to implement
> zext.w with rs2 set as ZERO.
> 
> Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
> ---
>  arch/riscv/Kconfig       | 19 +++++++++++++++++++
>  arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++
>  2 files changed, 37 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 6bec1bce6586..0679127cc0ea 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -586,6 +586,14 @@ config RISCV_ISA_V_PREEMPTIVE
>  	  preemption. Enabling this config will result in higher memory
>  	  consumption due to the allocation of per-task's kernel Vector context.
>  
> +config TOOLCHAIN_HAS_ZBA
> +	bool
> +	default y
> +	depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
> +	depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
> +	depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
> +	depends on AS_HAS_OPTION_ARCH
> +
>  config TOOLCHAIN_HAS_ZBB
>  	bool
>  	default y
> @@ -601,6 +609,17 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO
>  	def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb)
>  	depends on AS_HAS_OPTION_ARCH
>  
> +config RISCV_ISA_ZBA
> +	bool "Zba extension support for bit manipulation instructions"
> +	depends on TOOLCHAIN_HAS_ZBA
> +	depends on RISCV_ALTERNATIVE
> +	default y
> +	help
> +	   Adds support to dynamically detect the presence of the ZBA
> +	   extension (address generation acceleration) and enable its usage.

Recently I sent some patches to reword other extensions' help text,
because the "add support to dynamically detect" had confused people a
bit. Dynamic detection is done regardless of config options for Zba.
The wording I went with in my patch for Zbb was:
	   Add support for enabling optimisations in the kernel when the
	   Zbb extension is detected at boot.
Could you use something similar here in the opening sentence please?

Thanks,
Conor.

[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 161 bytes --]

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RE: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension

[Wang, Xiao W]

> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: Saturday, May 11, 2024 4:56 AM
> To: Wang, Xiao W <xiao.w.wang@intel.com>
> Cc: paul.walmsley@sifive.com; palmer@dabbelt.com;
> aou@eecs.berkeley.edu; luke.r.nels@gmail.com; xi.wang@gmail.com;
> bjorn@kernel.org; ast@kernel.org; daniel@iogearbox.net; andrii@kernel.org;
> martin.lau@linux.dev; eddyz87@gmail.com; song@kernel.org;
> yonghong.song@linux.dev; john.fastabend@gmail.com; kpsingh@kernel.org;
> sdf@google.com; haoluo@google.com; jolsa@kernel.org; linux-
> riscv@lists.infradead.org; linux-kernel@vger.kernel.org; bpf@vger.kernel.org;
> pulehui@huawei.com; Li, Haicheng <haicheng.li@intel.com>
> Subject: Re: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension
> 
> On Tue, May 07, 2024 at 06:45:28PM +0800, Xiao Wang wrote:
> > The Zba extension provides add.uw insn which can be used to implement
> > zext.w with rs2 set as ZERO.
> >
> > Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
> > ---
> >  arch/riscv/Kconfig       | 19 +++++++++++++++++++
> >  arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++
> >  2 files changed, 37 insertions(+)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 6bec1bce6586..0679127cc0ea 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -586,6 +586,14 @@ config RISCV_ISA_V_PREEMPTIVE
> >  	  preemption. Enabling this config will result in higher memory
> >  	  consumption due to the allocation of per-task's kernel Vector
> context.
> >
> > +config TOOLCHAIN_HAS_ZBA
> > +	bool
> > +	default y
> > +	depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
> > +	depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
> > +	depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
> > +	depends on AS_HAS_OPTION_ARCH
> > +
> >  config TOOLCHAIN_HAS_ZBB
> >  	bool
> >  	default y
> > @@ -601,6 +609,17 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO
> >  	def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb)
> >  	depends on AS_HAS_OPTION_ARCH
> >
> > +config RISCV_ISA_ZBA
> > +	bool "Zba extension support for bit manipulation instructions"
> > +	depends on TOOLCHAIN_HAS_ZBA
> > +	depends on RISCV_ALTERNATIVE
> > +	default y
> > +	help
> > +	   Adds support to dynamically detect the presence of the ZBA
> > +	   extension (address generation acceleration) and enable its usage.
> 
> Recently I sent some patches to reword other extensions' help text,
> because the "add support to dynamically detect" had confused people a
> bit. Dynamic detection is done regardless of config options for Zba.
> The wording I went with in my patch for Zbb was:
> 	   Add support for enabling optimisations in the kernel when the
> 	   Zbb extension is detected at boot.
> Could you use something similar here in the opening sentence please?

Agree with you. Yes, I would reword it in next version.

Thanks,
Xiao

> 
> Thanks,
> Conor.

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