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Mon, 27 May 2024 09:29:36 -0700 (PDT) Received: from localhost ([176.74.158.132]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089b0410sm113439735e9.29.2024.05.27.09.29.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 09:29:36 -0700 (PDT) Date: Mon, 27 May 2024 18:29:35 +0200 From: Andrew Jones To: Yong-Xuan Wang Cc: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, greentime.hu@sifive.com, vincent.chen@sifive.com, cleger@rivosinc.com, alex@ghiti.fr, Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v4 4/5] RISC-V: KVM: add support for SBI_FWFT_PTE_AD_HW_UPDATING Message-ID: <20240527-cd06bb4215d05129f4793dd6@orel> References: <20240524103307.2684-1-yongxuan.wang@sifive.com> <20240524103307.2684-5-yongxuan.wang@sifive.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240524103307.2684-5-yongxuan.wang@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240527_092939_177297_F8383A1E X-CRM114-Status: GOOD ( 20.48 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, May 24, 2024 at 06:33:04PM GMT, Yong-Xuan Wang wrote: > Add support for SBI_FWFT_PTE_AD_HW_UPDATING to set the PTE A/D bits > updating behavior for Guest/VM. > > Signed-off-by: Yong-Xuan Wang > --- > arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h | 2 +- > arch/riscv/kvm/vcpu_sbi_fwft.c | 38 +++++++++++++++++++++- > 2 files changed, 38 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h b/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h > index 7b7bcc5c8fee..3614a44e0a4a 100644 > --- a/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h > +++ b/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h > @@ -11,7 +11,7 @@ > > #include > > -#define KVM_SBI_FWFT_FEATURE_COUNT 1 > +#define KVM_SBI_FWFT_FEATURE_COUNT 2 > > struct kvm_sbi_fwft_config; > struct kvm_vcpu; > diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c > index 89ec263c250d..14ef74023340 100644 > --- a/arch/riscv/kvm/vcpu_sbi_fwft.c > +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c > @@ -71,6 +71,36 @@ static int kvm_sbi_fwft_get_misaligned_delegation(struct kvm_vcpu *vcpu, > return SBI_SUCCESS; > } > > +static int kvm_sbi_fwft_adue_supported(struct kvm_vcpu *vcpu) > +{ > + if (!riscv_isa_extension_available(vcpu->arch.isa, SVADU)) > + return SBI_ERR_NOT_SUPPORTED; > + > + return 0; > +} > + > +static int kvm_sbi_fwft_set_adue(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, > + unsigned long value) > +{ > + if (value) > + vcpu->arch.cfg.henvcfg |= ENVCFG_ADUE; > + else > + vcpu->arch.cfg.henvcfg &= ~ENVCFG_ADUE; > + > + return SBI_SUCCESS; > +} > + > +static int kvm_sbi_fwft_get_adue(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, > + unsigned long *value) > +{ > + if (!riscv_isa_extension_available(vcpu->arch.isa, SVADU)) > + return SBI_ERR_NOT_SUPPORTED; > + > + *value = !!(vcpu->arch.cfg.henvcfg & ENVCFG_ADUE); > + > + return SBI_SUCCESS; > +} > + > static struct kvm_sbi_fwft_config * > kvm_sbi_fwft_get_config(struct kvm_vcpu *vcpu, enum sbi_fwft_feature_t feature) > { > @@ -177,7 +207,13 @@ static const struct kvm_sbi_fwft_feature features[] = { > .supported = kvm_sbi_fwft_misaligned_delegation_supported, > .set = kvm_sbi_fwft_set_misaligned_delegation, > .get = kvm_sbi_fwft_get_misaligned_delegation, > - } > + }, > + { > + .id = SBI_FWFT_PTE_AD_HW_UPDATING, > + .supported = kvm_sbi_fwft_adue_supported, > + .set = kvm_sbi_fwft_set_adue, > + .get = kvm_sbi_fwft_get_adue, > + }, > }; > > static_assert(ARRAY_SIZE(features) == KVM_SBI_FWFT_FEATURE_COUNT); > -- > 2.17.1 > > Reviewed-by: Andrew Jones _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv