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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57aadf9e093sm7201840a12.13.2024.06.10.04.06.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jun 2024 04:06:10 -0700 (PDT) Date: Mon, 10 Jun 2024 13:06:09 +0200 From: Andrew Jones To: Tomasz Jeznach Subject: Re: [PATCH v7 6/7] iommu/riscv: Command and fault queue support Message-ID: <20240610-3cd1ba07c1b488a451dd7ddd@orel> References: <422f66285da1b164466b223f83d7f06564968f09.1717612299.git.tjeznach@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <422f66285da1b164466b223f83d7f06564968f09.1717612299.git.tjeznach@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240610_040614_019908_0AB7B335 X-CRM114-Status: GOOD ( 13.38 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , devicetree@vger.kernel.org, Conor Dooley , Albert Ou , linux@rivosinc.com, Will Deacon , Joerg Roedel , linux-kernel@vger.kernel.org, Rob Herring , Sebastien Boeuf , iommu@lists.linux.dev, Palmer Dabbelt , Zong Li , Paul Walmsley , Nick Kossifidis , Krzysztof Kozlowski , Robin Murphy , linux-riscv@lists.infradead.org, Lu Baolu Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Jun 05, 2024 at 12:57:48PM GMT, Tomasz Jeznach wrote: ... > +static int riscv_iommu_queue_alloc(struct riscv_iommu_device *iommu, > + struct riscv_iommu_queue *queue, > + size_t entry_size) > +{ > + unsigned int logsz; > + u64 qb, rb; > + > + /* > + * Use WARL base register property to discover maximum allowed > + * number of entries and optional fixed IO address for queue location. > + */ > + riscv_iommu_writeq(iommu, queue->qbr, RISCV_IOMMU_QUEUE_LOG2SZ_FIELD); > + qb = riscv_iommu_readq(iommu, queue->qbr); > + > + /* > + * Calculate and verify hardware supported queue length, as reported > + * by the field LOG2SZ, where max queue length is equal to 2^(LOG2SZ + 1). > + * Update queue size based on hardware supported value. > + */ > + logsz = ilog2(queue->mask); > + if (logsz > FIELD_GET(RISCV_IOMMU_QUEUE_LOG2SZ_FIELD, qb)) > + logsz = FIELD_GET(RISCV_IOMMU_QUEUE_LOG2SZ_FIELD, qb); > + > + /* > + * Use WARL base register property to discover an optional fixed IO > + * address for queue ring buffer location. Otherwise allocate contiguous > + * system memory. > + */ > + if (FIELD_GET(RISCV_IOMMU_PPN_FIELD, qb)) { > + const size_t queue_size = entry_size << (logsz + 1); > + > + queue->phys = ppn_to_phys(FIELD_GET(RISCV_IOMMU_PPN_FIELD, qb)); Shouldn't this be something like FIELD_GET(RISCV_IOMMU_PPN_FIELD, qb) << PAGE_SHIFT ppn_to_phys() assumes the ppn it's converting to be shifted up by 10, but FIELD_GET has shifted it down to zero. Thanks, drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv