Re: [PATCH v1 2/9] dt-bindings: riscv: Add SpacemiT X60 compatibles

Conor Dooley
2024-06-18T15:45:59Z

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On Mon, Jun 17, 2024 at 01:20:47AM +0800, Yangyu Chen wrote:
> The X60 is RISC-V CPU cores from SpacemiT and currently used in their K1
> SoC.
>
> Link: https://www.spacemit.com/en/spacemit-x60-core/
>

nit: Delete the blank line

> Signed-off-by: Yangyu Chen <cyy@cyyself.name>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index d87dd50f1a4b..5ad9cb410335 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -46,6 +46,7 @@ properties:
> - sifive,u7
> - sifive,u74
> - sifive,u74-mc
> + - spacemit,x60
> - thead,c906
> - thead,c910
> - thead,c920
> --
> 2.45.1
>

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