From: Jason Gunthorpe <jgg@ziepe.ca>
To: Zong Li <zong.li@sifive.com>
Cc: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com,
tjeznach@rivosinc.com, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu, kevin.tian@intel.com,
linux-kernel@vger.kernel.org, iommu@lists.linux.dev,
linux-riscv@lists.infradead.org
Subject: Re: [RFC PATCH v2 08/10] iommu/riscv: support nested iommu for flushing cache
Date: Wed, 19 Jun 2024 13:17:40 -0300 [thread overview]
Message-ID: <20240619161740.GP1091770@ziepe.ca> (raw)
In-Reply-To: <20240614142156.29420-9-zong.li@sifive.com>
On Fri, Jun 14, 2024 at 10:21:54PM +0800, Zong Li wrote:
> This patch implements cache_invalidate_user operation for the userspace
> to flush the hardware caches for a nested domain through iommufd.
>
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
> drivers/iommu/riscv/iommu.c | 90 ++++++++++++++++++++++++++++++++++--
> include/uapi/linux/iommufd.h | 11 +++++
> 2 files changed, 97 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
> index 410b236e9b24..d08eb0a2939e 100644
> --- a/drivers/iommu/riscv/iommu.c
> +++ b/drivers/iommu/riscv/iommu.c
> @@ -1587,8 +1587,9 @@ static int riscv_iommu_attach_dev_nested(struct iommu_domain *domain, struct dev
> if (riscv_iommu_bond_link(riscv_domain, dev))
> return -ENOMEM;
>
> - riscv_iommu_iotlb_inval(riscv_domain, 0, ULONG_MAX);
> - info->dc_user.ta |= RISCV_IOMMU_PC_TA_V;
> + if (riscv_iommu_bond_link(info->domain, dev))
> + return -ENOMEM;
?? Is this in the wrong patch then? Confused
> riscv_iommu_iodir_update(iommu, dev, &info->dc_user);
>
> info->domain = riscv_domain;
> @@ -1611,13 +1612,92 @@ static void riscv_iommu_domain_free_nested(struct iommu_domain *domain)
> kfree(riscv_domain);
> }
>
> +static int riscv_iommu_fix_user_cmd(struct riscv_iommu_command *cmd,
> + unsigned int pscid, unsigned int gscid)
> +{
> + u32 opcode = FIELD_GET(RISCV_IOMMU_CMD_OPCODE, cmd->dword0);
> +
> + switch (opcode) {
> + case RISCV_IOMMU_CMD_IOTINVAL_OPCODE:
> + u32 func = FIELD_GET(RISCV_IOMMU_CMD_FUNC, cmd->dword0);
> +
> + if (func != RISCV_IOMMU_CMD_IOTINVAL_FUNC_GVMA &&
> + func != RISCV_IOMMU_CMD_IOTINVAL_FUNC_VMA) {
> + pr_warn("The IOTINVAL function: 0x%x is not supported\n",
> + func);
> + return -EOPNOTSUPP;
> + }
> +
> + if (func == RISCV_IOMMU_CMD_IOTINVAL_FUNC_GVMA) {
> + cmd->dword0 &= ~RISCV_IOMMU_CMD_FUNC;
> + cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_FUNC,
> + RISCV_IOMMU_CMD_IOTINVAL_FUNC_VMA);
> + }
> +
> + cmd->dword0 &= ~(RISCV_IOMMU_CMD_IOTINVAL_PSCID |
> + RISCV_IOMMU_CMD_IOTINVAL_GSCID);
> + riscv_iommu_cmd_inval_set_pscid(cmd, pscid);
> + riscv_iommu_cmd_inval_set_gscid(cmd, gscid);
> + break;
> + case RISCV_IOMMU_CMD_IODIR_OPCODE:
> + /*
> + * Ensure the device ID is right. We expect that VMM has
> + * transferred the device ID to host's from guest's.
> + */
I'm not sure what this remark means, but I expect you will need to
translate any devices IDs from virtual to physical.
>
> static int
> -riscv_iommu_get_dc_user(struct device *dev, struct iommu_hwpt_riscv_iommu *user_arg)
> +riscv_iommu_get_dc_user(struct device *dev, struct iommu_hwpt_riscv_iommu *user_arg,
> + struct riscv_iommu_domain *s1_domain)
> {
> struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
> struct riscv_iommu_device *iommu = dev_to_iommu(dev);
> @@ -1663,6 +1743,8 @@ riscv_iommu_get_dc_user(struct device *dev, struct iommu_hwpt_riscv_iommu *user_
> riscv_iommu_get_dc(iommu, fwspec->ids[i]),
> sizeof(struct riscv_iommu_dc));
> info->dc_user.fsc = dc.fsc;
> + info->dc_user.ta = FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, s1_domain->pscid) |
> + RISCV_IOMMU_PC_TA_V;
> }
It is really weird that the s1 domain has any kind of id. What is the
PSCID? Is it analogous to VMID on ARM?
Jason
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next prev parent reply other threads:[~2024-06-19 16:17 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-14 14:21 [RFC PATCH v2 00/10] RISC-V IOMMU HPM and nested IOMMU support Zong Li
2024-06-14 14:21 ` [RFC PATCH v2 01/10] iommu/riscv: add RISC-V IOMMU PMU support Zong Li
2024-06-17 14:55 ` Jason Gunthorpe
2024-06-18 1:14 ` Zong Li
2024-06-14 14:21 ` [RFC PATCH v2 02/10] iommu/riscv: support HPM and interrupt handling Zong Li
2024-12-10 7:54 ` [External] " yunhui cui
2024-12-10 8:48 ` Xu Lu
2024-12-27 8:37 ` Zong Li
2025-09-01 13:36 ` [RFC PATCH v2 00/10] RISC-V IOMMU HPM and nested IOMMU support niliqiang
2025-09-02 4:01 ` Zong Li
2025-09-05 3:27 ` Zong Li
2024-06-14 14:21 ` [RFC PATCH v2 03/10] iommu/riscv: use data structure instead of individual values Zong Li
2024-06-14 14:21 ` [RFC PATCH v2 04/10] iommu/riscv: add iotlb_sync_map operation support Zong Li
2024-06-15 3:14 ` Baolu Lu
2024-06-17 13:43 ` Zong Li
2024-06-17 14:39 ` Jason Gunthorpe
2024-06-18 3:01 ` Zong Li
2024-06-18 13:31 ` Jason Gunthorpe
2024-06-14 14:21 ` [RFC PATCH v2 05/10] iommu/riscv: support GSCID and GVMA invalidation command Zong Li
2024-06-14 14:21 ` [RFC PATCH v2 06/10] iommu/riscv: support nested iommu for getting iommu hardware information Zong Li
2024-06-19 15:49 ` Jason Gunthorpe
2024-06-21 7:32 ` Zong Li
2024-06-14 14:21 ` [RFC PATCH v2 07/10] iommu/riscv: support nested iommu for creating domains owned by userspace Zong Li
2024-06-19 16:02 ` Jason Gunthorpe
2024-06-28 9:03 ` Zong Li
2024-06-28 22:32 ` Jason Gunthorpe
2024-06-19 16:34 ` Joao Martins
2024-06-21 7:34 ` Zong Li
2024-06-14 14:21 ` [RFC PATCH v2 08/10] iommu/riscv: support nested iommu for flushing cache Zong Li
2024-06-15 3:22 ` Baolu Lu
2024-06-17 2:16 ` Zong Li
2024-06-19 16:17 ` Jason Gunthorpe [this message]
2024-06-28 8:19 ` Zong Li
2024-06-28 22:26 ` Jason Gunthorpe
2024-06-14 14:21 ` [RFC PATCH v2 09/10] iommu/dma: Support MSIs through nested domains Zong Li
2024-06-14 18:12 ` Nicolin Chen
2024-06-17 2:15 ` Zong Li
2024-06-14 14:21 ` [RFC PATCH v2 10/10] iommu:riscv: support nested iommu for get_msi_mapping_domain operation Zong Li
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