From: Atish Patra <atishp@rivosinc.com>
To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org
Cc: Atish Patra <atishp@atishpatra.org>,
Anup Patel <anup@brainfault.org>, Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Jones <ajones@ventanamicro.com>,
Conor Dooley <conor.dooley@microchip.com>,
Samuel Holland <samuel.holland@sifive.com>,
Palmer Dabbelt <palmer@rivosinc.com>,
Alexandre Ghiti <alexghiti@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
Atish Patra <atishp@rivosinc.com>,
garthlei@pku.edu.cn
Subject: [PATCH v4 1/3] drivers/perf: riscv: Do not update the event data if uptodate
Date: Fri, 28 Jun 2024 00:51:41 -0700 [thread overview]
Message-ID: <20240628-misc_perf_fixes-v4-1-e01cfddcf035@rivosinc.com> (raw)
In-Reply-To: <20240628-misc_perf_fixes-v4-0-e01cfddcf035@rivosinc.com>
In case of an counter overflow, the event data may get corrupted
if called from an external overflow handler. This happens because
we can't update the counter without starting it when SBI PMU
extension is in use. However, the prev_count has been already
updated at the first pass while the counter value is still the
old one.
The solution is simple where we don't need to update it again
if it is already updated which can be detected using hwc state.
The event state in the overflow handler is updated in the following
patch. Thus, this fix can't be backported to kernel version where
overflow support was added.
Fixes: a8625217a054 ("drivers/perf: riscv: Implement SBI PMU snapshot function")
Reported-by: garthlei@pku.edu.cn
Closes:https://lore.kernel.org/all/CC51D53B-846C-4D81-86FC-FBF969D0A0D6@pku.edu.cn/
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
drivers/perf/riscv_pmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c
index 78c490e0505a..0a02e85a8951 100644
--- a/drivers/perf/riscv_pmu.c
+++ b/drivers/perf/riscv_pmu.c
@@ -167,7 +167,7 @@ u64 riscv_pmu_event_update(struct perf_event *event)
unsigned long cmask;
u64 oldval, delta;
- if (!rvpmu->ctr_read)
+ if (!rvpmu->ctr_read || (hwc->state & PERF_HES_UPTODATE))
return 0;
cmask = riscv_pmu_ctr_get_width_mask(event);
--
2.34.1
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next prev parent reply other threads:[~2024-06-28 7:52 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-28 7:51 [PATCH v4 0/3] Assorted fixes in RISC-V PMU driver Atish Patra
2024-06-28 7:51 ` Atish Patra [this message]
2024-06-28 7:51 ` [PATCH v4 2/3] drivers/perf: riscv: Reset the counter to hpmevent mapping while starting cpus Atish Patra
2024-06-28 7:51 ` [PATCH v4 3/3] perf: RISC-V: Check standard event availability Atish Patra
2024-07-01 13:01 ` [PATCH v4 0/3] Assorted fixes in RISC-V PMU driver Will Deacon
2024-07-03 19:59 ` Palmer Dabbelt
2024-07-04 13:10 ` patchwork-bot+linux-riscv
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