From: Xiao Wang <xiao.w.wang@intel.com>
To: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, atishp@atishpatra.org
Cc: anup@brainfault.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, Xiao Wang <xiao.w.wang@intel.com>
Subject: [PATCH] drivers/perf: riscv: Remove redundant macro check
Date: Mon, 8 Jul 2024 20:12:24 +0800 [thread overview]
Message-ID: <20240708121224.1148154-1-xiao.w.wang@intel.com> (raw)
The macro CONFIG_RISCV_PMU must have been defined when riscv_pmu.c gets
compiled, so this patch removes the redundant check.
Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
---
drivers/perf/riscv_pmu.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c
index 0a02e85a8951..7644147d50b4 100644
--- a/drivers/perf/riscv_pmu.c
+++ b/drivers/perf/riscv_pmu.c
@@ -39,7 +39,6 @@ void arch_perf_update_userpage(struct perf_event *event,
userpg->cap_user_time_short = 0;
userpg->cap_user_rdpmc = riscv_perf_user_access(event);
-#ifdef CONFIG_RISCV_PMU
/*
* The counters are 64-bit but the priv spec doesn't mandate all the
* bits to be implemented: that's why, counter width can vary based on
@@ -47,7 +46,6 @@ void arch_perf_update_userpage(struct perf_event *event,
*/
if (userpg->cap_user_rdpmc)
userpg->pmc_width = to_riscv_pmu(event->pmu)->ctr_get_width(event->hw.idx) + 1;
-#endif
do {
rd = sched_clock_read_begin(&seq);
--
2.25.1
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next reply other threads:[~2024-07-08 12:04 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-08 12:12 Xiao Wang [this message]
2024-07-08 12:22 ` [PATCH] drivers/perf: riscv: Remove redundant macro check Conor Dooley
2024-07-09 20:29 ` Charlie Jenkins
2024-07-09 20:44 ` Conor Dooley
2024-07-09 20:57 ` Charlie Jenkins
2024-07-09 21:04 ` Conor Dooley
2024-07-09 21:43 ` Atish Patra
2024-07-10 6:03 ` Wang, Xiao W
2024-09-17 13:00 ` patchwork-bot+linux-riscv
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