From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Charlie Jenkins <charlie@rivosinc.com>,
Deepak Gupta <debug@rivosinc.com>,
Clement Leger <cleger@rivosinc.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 6/7] riscv: staticalize and remove asmlinkage from updated functions
Date: Sun, 21 Jul 2024 01:12:31 +0800 [thread overview]
Message-ID: <20240720171232.1753-7-jszhang@kernel.org> (raw)
In-Reply-To: <20240720171232.1753-1-jszhang@kernel.org>
Now that the callers of these functions have moved into C, they
are only called in trap.c and no longer need the asmlinkage
annotation. So make them static and remove asmlinkage from them.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/include/asm/asm-prototypes.h | 19 +------------------
arch/riscv/kernel/kernel_mode_vector.c | 2 +-
arch/riscv/kernel/traps.c | 16 ++++++++--------
3 files changed, 10 insertions(+), 27 deletions(-)
diff --git a/arch/riscv/include/asm/asm-prototypes.h b/arch/riscv/include/asm/asm-prototypes.h
index c6691e9032dd..067e93e3b400 100644
--- a/arch/riscv/include/asm/asm-prototypes.h
+++ b/arch/riscv/include/asm/asm-prototypes.h
@@ -31,30 +31,13 @@ void xor_regs_5_(unsigned long bytes, unsigned long *__restrict p1,
const unsigned long *__restrict p5);
#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE
-asmlinkage void riscv_v_context_nesting_start(struct pt_regs *regs);
+void riscv_v_context_nesting_start(struct pt_regs *regs);
asmlinkage void riscv_v_context_nesting_end(struct pt_regs *regs);
#endif /* CONFIG_RISCV_ISA_V_PREEMPTIVE */
#endif /* CONFIG_RISCV_ISA_V */
-#define DECLARE_DO_ERROR_INFO(name) asmlinkage void name(struct pt_regs *regs)
-
-DECLARE_DO_ERROR_INFO(do_trap_unknown);
-DECLARE_DO_ERROR_INFO(do_trap_insn_misaligned);
-DECLARE_DO_ERROR_INFO(do_trap_insn_fault);
-DECLARE_DO_ERROR_INFO(do_trap_insn_illegal);
-DECLARE_DO_ERROR_INFO(do_trap_load_fault);
-DECLARE_DO_ERROR_INFO(do_trap_load_misaligned);
-DECLARE_DO_ERROR_INFO(do_trap_store_misaligned);
-DECLARE_DO_ERROR_INFO(do_trap_store_fault);
-DECLARE_DO_ERROR_INFO(do_trap_ecall_u);
-DECLARE_DO_ERROR_INFO(do_trap_ecall_s);
-DECLARE_DO_ERROR_INFO(do_trap_ecall_m);
-DECLARE_DO_ERROR_INFO(do_trap_break);
-
asmlinkage void handle_bad_stack(struct pt_regs *regs);
-asmlinkage void do_page_fault(struct pt_regs *regs);
-asmlinkage void do_irq(struct pt_regs *regs);
asmlinkage void do_traps(struct pt_regs *regs, unsigned long cause);
#endif /* _ASM_RISCV_PROTOTYPES_H */
diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/kernel_mode_vector.c
index 6afe80c7f03a..a6995429ddf5 100644
--- a/arch/riscv/kernel/kernel_mode_vector.c
+++ b/arch/riscv/kernel/kernel_mode_vector.c
@@ -152,7 +152,7 @@ static int riscv_v_start_kernel_context(bool *is_nested)
}
/* low-level V context handling code, called with irq disabled */
-asmlinkage void riscv_v_context_nesting_start(struct pt_regs *regs)
+void riscv_v_context_nesting_start(struct pt_regs *regs)
{
int depth;
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index 3eaa7c72f2be..dc1bc84cfe15 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -147,7 +147,7 @@ static void do_trap_error(struct pt_regs *regs, int signo, int code,
#define __trap_section noinstr
#endif
#define DO_ERROR_INFO(name, signo, code, str) \
-asmlinkage __trap_section void name(struct pt_regs *regs) \
+static __trap_section void name(struct pt_regs *regs) \
{ \
if (user_mode(regs)) { \
irqentry_enter_from_user_mode(regs); \
@@ -167,7 +167,7 @@ DO_ERROR_INFO(do_trap_insn_misaligned,
DO_ERROR_INFO(do_trap_insn_fault,
SIGSEGV, SEGV_ACCERR, "instruction access fault");
-asmlinkage __trap_section void do_trap_insn_illegal(struct pt_regs *regs)
+static __trap_section void do_trap_insn_illegal(struct pt_regs *regs)
{
bool handled;
@@ -198,7 +198,7 @@ asmlinkage __trap_section void do_trap_insn_illegal(struct pt_regs *regs)
DO_ERROR_INFO(do_trap_load_fault,
SIGSEGV, SEGV_ACCERR, "load access fault");
-asmlinkage __trap_section void do_trap_load_misaligned(struct pt_regs *regs)
+static __trap_section void do_trap_load_misaligned(struct pt_regs *regs)
{
if (user_mode(regs)) {
irqentry_enter_from_user_mode(regs);
@@ -219,7 +219,7 @@ asmlinkage __trap_section void do_trap_load_misaligned(struct pt_regs *regs)
}
}
-asmlinkage __trap_section void do_trap_store_misaligned(struct pt_regs *regs)
+static __trap_section void do_trap_store_misaligned(struct pt_regs *regs)
{
if (user_mode(regs)) {
irqentry_enter_from_user_mode(regs);
@@ -294,7 +294,7 @@ static void handle_break(struct pt_regs *regs)
die(regs, "Kernel BUG");
}
-asmlinkage __trap_section void do_trap_break(struct pt_regs *regs)
+static __trap_section void do_trap_break(struct pt_regs *regs)
{
if (user_mode(regs)) {
irqentry_enter_from_user_mode(regs);
@@ -311,7 +311,7 @@ asmlinkage __trap_section void do_trap_break(struct pt_regs *regs)
}
}
-asmlinkage __trap_section __no_stack_protector
+static __trap_section __no_stack_protector
void do_trap_ecall_u(struct pt_regs *regs)
{
if (user_mode(regs)) {
@@ -355,7 +355,7 @@ void do_trap_ecall_u(struct pt_regs *regs)
}
#ifdef CONFIG_MMU
-asmlinkage noinstr void do_page_fault(struct pt_regs *regs)
+static noinstr void do_page_fault(struct pt_regs *regs)
{
irqentry_state_t state = irqentry_enter(regs);
@@ -378,7 +378,7 @@ static void noinstr handle_riscv_irq(struct pt_regs *regs)
irq_exit_rcu();
}
-asmlinkage void noinstr do_irq(struct pt_regs *regs)
+static void noinstr do_irq(struct pt_regs *regs)
{
irqentry_state_t state = irqentry_enter(regs);
--
2.43.0
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next prev parent reply other threads:[~2024-07-20 17:27 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-20 17:12 [PATCH v2 0/7] riscv: convert bottom half of exception handling to C Jisheng Zhang
2024-07-20 17:12 ` [PATCH v2 1/7] riscv: traps: staticalize handle_break() Jisheng Zhang
2024-07-20 17:12 ` [PATCH v2 2/7] riscv: traps: remove __visible annotation Jisheng Zhang
2024-07-20 17:12 ` [PATCH v2 3/7] riscv: convert bottom half of exception handling to C Jisheng Zhang
2024-11-26 0:08 ` Deepak Gupta
2024-07-20 17:12 ` [PATCH v2 4/7] riscv: errata: remove ALT_INSN_FAULT and ALT_PAGE_FAULT Jisheng Zhang
2024-07-20 17:12 ` [PATCH v2 5/7] riscv: errata: sifive: remove NOMMU handling Jisheng Zhang
2024-07-20 17:12 ` Jisheng Zhang [this message]
2024-07-20 17:12 ` [PATCH v2 7/7] riscv: traps: mark do_irq() as __always_inline Jisheng Zhang
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