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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7acab53704sm645196066b.86.2024.07.30.06.14.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jul 2024 06:14:40 -0700 (PDT) Date: Tue, 30 Jul 2024 15:14:39 +0200 From: Andrew Jones To: Andy Chiu Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, bjorn@kernel.org, debug@rivosinc.com, Paul Walmsley , Albert Ou , Conor Dooley , =?utf-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= , Evan Green , Charlie Jenkins , samuel.holland@sifive.com Subject: Re: [PATCH] riscv: fix isa validation for virtual [ms]envcfg extension Message-ID: <20240730-bcf30b29609f33dae538f26d@orel> References: <20240730073847.1999420-1-andy.chiu@sifive.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240730073847.1999420-1-andy.chiu@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240730_061444_553836_08E86329 X-CRM114-Status: GOOD ( 23.09 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Jul 30, 2024 at 03:38:45PM GMT, Andy Chiu wrote: > The exntension RISCV_ISA_EXT_XLINUXENVCFG was accidentally turned off > after introducing ISA validation. The reason is that this extension is > not in the riscv_isa_ext[] list, causing riscv_get_isa_ext_data() fail > to find a corresponding riscv_isa_ext_data pointer. As a result, the > kernel skipped setting resolved_isa bitmask. To fix this, we proceed > with the bit information obtained from source_isa bitmask. This means > that the bit in resolved_isa is set unconditionally, regardless of > whether we find an entry from riscv_isa_ext[] list. This should be safe > as the kernel already parse isa string before writing into source_isa. > > Fixes: 625034abd52a ("riscv: add ISA extensions validation callback") > Signed-off-by: Andy Chiu > --- > arch/riscv/kernel/cpufeature.c | 13 +++++-------- > 1 file changed, 5 insertions(+), 8 deletions(-) > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 8f20607adb40..3f91a1f39a50 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -432,10 +432,7 @@ static void __init riscv_resolve_isa(unsigned long *source_isa, > bitmap_copy(prev_resolved_isa, resolved_isa, RISCV_ISA_EXT_MAX); > for_each_set_bit(bit, source_isa, RISCV_ISA_EXT_MAX) { > ext = riscv_get_isa_ext_data(bit); > - if (!ext) > - continue; > - > - if (ext->validate) { > + if (ext && ext->validate) { > ret = ext->validate(ext, resolved_isa); > if (ret == -EPROBE_DEFER) { > loop = true; > @@ -447,13 +444,13 @@ static void __init riscv_resolve_isa(unsigned long *source_isa, > } > } > > - set_bit(ext->id, resolved_isa); > + set_bit(bit, resolved_isa); > /* No need to keep it in source isa now that it is enabled */ > - clear_bit(ext->id, source_isa); > + clear_bit(bit, source_isa); > > /* Single letter extensions get set in hwcap */ > - if (ext->id < RISCV_ISA_EXT_BASE) > - *this_hwcap |= isa2hwcap[ext->id]; > + if (bit < RISCV_ISA_EXT_BASE) > + *this_hwcap |= isa2hwcap[bit]; > } > } while (loop && memcmp(prev_resolved_isa, resolved_isa, sizeof(prev_resolved_isa))); > } > -- > 2.43.0 > Hi Andy, This looks like the same solution that Samuel sent which is currently under discussion[1]. [1] https://lore.kernel.org/all/20240718213011.2600150-1-samuel.holland@sifive.com/ Thanks, drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv