[PATCH 2/2] dt-bindings: riscv: Add Zicclsm ISA extension description.

Jesse Taube
2024-08-09T16:23:29Z

Add description for Zicclsm ISA extension.

Signed-off-by: Jesse Taube <jesse@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
V1 -> V2:
- New patch
V2 -> V3:
- No changes
V3 -> V4:
- No changes
V4 -> V5:
- No changes
V5 -> V6:
- No changes
V6 -> V7:
- No changes
V7 -> V8:
- Rebase onto 2d1f51d8a4b0 (palmer/for-next)
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index a06dbc6b4928..d06ee82abcc1 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -361,6 +361,13 @@ properties:
The standard Zicboz extension for cache-block zeroing as ratified
in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.

+ - const: zicclsm
+ description:
+ The standard Zicclsm extension for misaligned support for all regular
+ load and store instructions (including scalar and vector) but not AMOs
+ or other specialized forms of memory access. Defined in the
+ RISC-V RVA Profiles Specification.
+
- const: zicntr
description:
The standard Zicntr extension for base counters and timers, as
--
2.45.2