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[31.30.173.13]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8679a8e3f9sm86081266b.1.2024.08.21.07.11.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Aug 2024 07:11:33 -0700 (PDT) Date: Wed, 21 Aug 2024 16:11:32 +0200 From: Andrew Jones To: Alexandre Ghiti Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Andrea Parri , Nathan Chancellor , Peter Zijlstra , Ingo Molnar , Will Deacon , Waiman Long , Boqun Feng , Arnd Bergmann , Leonardo Bras , Guo Ren , linux-doc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org Subject: Re: [PATCH v5 02/13] riscv: Do not fail to build on byte/halfword operations with Zawrs Message-ID: <20240821-ab85a511044c72f0511f7a1e@orel> References: <20240818063538.6651-1-alexghiti@rivosinc.com> <20240818063538.6651-3-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240818063538.6651-3-alexghiti@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240821_071136_986241_09607237 X-CRM114-Status: GOOD ( 17.04 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sun, Aug 18, 2024 at 08:35:27AM GMT, Alexandre Ghiti wrote: > riscv does not have lr instructions on byte and halfword but the > qspinlock implementation actually uses such atomics provided by the > Zabha extension, so those sizes are legitimate. > > Then instead of failing to build, just fallback to the !Zawrs path. > > Signed-off-by: Alexandre Ghiti > --- > arch/riscv/include/asm/cmpxchg.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h > index ebbce134917c..ac1d7df898ef 100644 > --- a/arch/riscv/include/asm/cmpxchg.h > +++ b/arch/riscv/include/asm/cmpxchg.h > @@ -245,6 +245,11 @@ static __always_inline void __cmpwait(volatile void *ptr, > : : : : no_zawrs); > > switch (size) { > + case 1: > + fallthrough; > + case 2: > + /* RISC-V doesn't have lr instructions on byte and half-word. */ > + goto no_zawrs; > case 4: > asm volatile( > " lr.w %0, %1\n" > -- > 2.39.2 > Reviewed-by: Andrew Jones _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv