From: Andrew Jones <ajones@ventanamicro.com>
To: Nick Hu <nick.hu@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>,
zong.li@sifive.com, "Rafael J. Wysocki" <rafael@kernel.org>,
linux-pm@vger.kernel.org,
Daniel Lezcano <daniel.lezcano@linaro.org>,
linux-kernel@vger.kernel.org,
Samuel Holland <samuel.holland@sifive.com>,
Conor Dooley <conor.dooley@microchip.com>,
Palmer Dabbelt <palmer@dabbelt.com>, Pavel Machek <pavel@ucw.cz>,
Paul Walmsley <paul.walmsley@sifive.com>,
greentime.hu@sifive.com, Thomas Gleixner <tglx@linutronix.de>,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH 1/2] riscv: Add stimecmp save and restore
Date: Thu, 29 Aug 2024 09:59:04 +0200 [thread overview]
Message-ID: <20240829-fb7bda6b46302b65b2f89d20@orel> (raw)
In-Reply-To: <20240829033904.477200-2-nick.hu@sifive.com>
On Thu, Aug 29, 2024 at 11:38:59AM GMT, Nick Hu wrote:
> If the HW support the SSTC extension, we should save and restore the
> stimecmp register while cpu non retention suspend.
>
> Signed-off-by: Nick Hu <nick.hu@sifive.com>
> ---
> arch/riscv/include/asm/suspend.h | 4 ++++
> arch/riscv/kernel/suspend.c | 13 +++++++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h
> index 4ffb022b097f..ffaac2efabb5 100644
> --- a/arch/riscv/include/asm/suspend.h
> +++ b/arch/riscv/include/asm/suspend.h
> @@ -16,6 +16,10 @@ struct suspend_context {
> unsigned long envcfg;
> unsigned long tvec;
> unsigned long ie;
> +#if __riscv_xlen < 64
> + unsigned long stimecmph;
> +#endif
I'm not sure the reduction in struct size is worth the #ifdeffery. If we
just always add stimecmph, then we can also change the #ifdef's below to
if's, i.e. if (__riscv_xlen < 64), which should still remove the code from
64-bit builds.
Or maybe we need something like
#if __riscv_xlen < 64
#define csrh_write(r, v) csr_write(r, v)
#else
#define csrh_write(r, v)
#endif
in asm/csr.h and then use it for all the *h csrs, but keep the #if in
the struct.
Thanks,
drew
> + unsigned long stimecmp;
> #ifdef CONFIG_MMU
> unsigned long satp;
> #endif
> diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c
> index c8cec0cc5833..3afd86e1abf7 100644
> --- a/arch/riscv/kernel/suspend.c
> +++ b/arch/riscv/kernel/suspend.c
> @@ -19,6 +19,12 @@ void suspend_save_csrs(struct suspend_context *context)
> context->tvec = csr_read(CSR_TVEC);
> context->ie = csr_read(CSR_IE);
>
> + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SSTC)) {
> + context->stimecmp = csr_read(CSR_STIMECMP);
> +#if __riscv_xlen < 64
> + context->stimecmph = csr_read(CSR_STIMECMPH);
> +#endif
> + }
> /*
> * No need to save/restore IP CSR (i.e. MIP or SIP) because:
> *
> @@ -42,6 +48,13 @@ void suspend_restore_csrs(struct suspend_context *context)
> csr_write(CSR_TVEC, context->tvec);
> csr_write(CSR_IE, context->ie);
>
> + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SSTC)) {
> + csr_write(CSR_STIMECMP, context->stimecmp);
> +#if __riscv_xlen < 64
> + csr_write(CSR_STIMECMPH, context->stimecmph);
> +#endif
> + }
> +
> #ifdef CONFIG_MMU
> csr_write(CSR_SATP, context->satp);
> #endif
> --
> 2.34.1
>
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next prev parent reply other threads:[~2024-08-29 7:59 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-29 3:38 [PATCH 0/2] Support SSTC while PM operations Nick Hu
2024-08-29 3:38 ` [PATCH 1/2] riscv: Add stimecmp save and restore Nick Hu
2024-08-29 5:18 ` Anup Patel
2024-08-29 6:16 ` Nick Hu
2024-08-29 7:59 ` Andrew Jones [this message]
2024-08-30 5:53 ` Nick Hu
2024-08-29 3:39 ` [PATCH 2/2] time-riscv: Stop stimecmp when cpu hotplug Nick Hu
2024-08-29 5:18 ` Anup Patel
2024-08-29 6:23 ` Nick Hu
2024-08-29 6:49 ` Anup Patel
2024-08-30 5:56 ` Nick Hu
2024-08-29 13:43 ` Thomas Gleixner
2024-08-30 5:56 ` Nick Hu
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