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[209.17.68.221]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-720bc31874bsm3986223b3a.213.2024.11.02.04.54.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Nov 2024 04:54:12 -0700 (PDT) Date: Sat, 2 Nov 2024 20:54:11 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Bjorn Helgaas Cc: Conor Dooley , linux-pci@vger.kernel.org, Conor Dooley , Daire McNamara , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v5 2/2] PCI: microchip: rework reg region handing to support using either instance 1 or 2 Message-ID: <20241102115411.GE2260768@rocinante> References: <20240814-outmost-untainted-cedd4adcd551@spud> <20241101195129.GA1318063@bhelgaas> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20241101195129.GA1318063@bhelgaas> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241102_045414_771752_AE709A19 X-CRM114-Status: GOOD ( 24.87 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hello, > > The PCI host controller on PolarFire SoC has multiple "instances", each > > with their own bridge and ctrl address spaces. The original binding has > > an "apb" register region, and it is expected to be set to the base > > address of the host controllers register space. Defines in the driver > > were used to compute the addresses of the bridge and ctrl address ranges > > corresponding to instance1. Some customers want to use instance0 however > > and that requires changing the defines in the driver, which is clearly > > not a portable solution. > > The subject mentions "instance 1 or 2". > > This paragraph implies adding support for "instance0" ("customers want > to use instance0"). > > The DT patch suggests that we're adding support for "instance2" > ("customers want to use instance2"). > > Both patches suggest that the existing support is for "instance 1". > > Maybe what's being added is "instance 2", and this commit log should > s/instance0/instance 2/ ? And probably s/instance1/instance 1/ so the > style is consistent? > > Is this a "pick one or the other but not both" situation, or does this > device support two independent PCIe controllers? > > I first thought this driver supported a single PCIe controller, and > you were adding support for a second independent controller. > > But the fact that you say "the [singular] host controller on > PolarFire", and you're not changing mc_host_probe() to call > pci_host_common_probe() more than once makes me think there is only a > single PCIe controller, and for some reason you can choose to operate > it using either register set 1 or register set 2. Conor, let me know if we need to clarify the commit log per Bjorn's questions. If so, then I will do it directly on the branch. Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv