[RFC PATCH 11/15] RISC-V: Define irqbypass vcpu_info

Andrew Jones
2024-11-14T16:19:18Z

The vcpu_info parameter to irq_set_vcpu_affinity() effectively
defines an arch specific IOMMU <=> hypervisor protocol. Provide
a definition for the RISCV IOMMU.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
---
arch/riscv/include/asm/irq.h | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h
index 7b038f3b7cb0..8588667cbb5f 100644
--- a/arch/riscv/include/asm/irq.h
+++ b/arch/riscv/include/asm/irq.h
@@ -23,6 +23,15 @@ void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void));

struct fwnode_handle *riscv_get_intc_hwnode(void);

+struct riscv_iommu_vcpu_info {
+ u64 msi_addr_pattern;
+ u64 msi_addr_mask;
+ u32 group_index_bits;
+ u32 group_index_shift;
+ u64 gpa;
+ u64 hpa;
+};
+
#ifdef CONFIG_ACPI

enum riscv_irqchip_type {
--
2.47.0