[PATCH v2 1/5] dt-bindings: pci: Add Sophgo SG2042 PCIe host

Chen Wang
2024-12-09T07:20:46Z

From: Chen Wang <unicorn_wang@outlook.com>

Add binding for Sophgo SG2042 PCIe host controller.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
.../bindings/pci/sophgo,sg2042-pcie-host.yaml | 141 ++++++++++++++++++
1 file changed, 141 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml

diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
new file mode 100644
index 000000000000..aec31ec97092
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
@@ -0,0 +1,141 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/sophgo,sg2042-pcie-host.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 PCIe Host (Cadence PCIe Wrapper)
+
+description:
+ Sophgo SG2042 PCIe host controller is based on the Cadence PCIe core.
+
+maintainers:
+ - Chen Wang <unicorn_wang@outlook.com>
+
+properties:
+ compatible:
+ const: sophgo,sg2042-pcie-host
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: reg
+ - const: cfg
+
+ vendor-id:
+ const: 0x1f1c
+
+ device-id:
+ const: 0x2042
+
+ msi:
+ type: object
+ $ref: /schemas/interrupt-controller/msi-controller.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ compatible:
+ items:
+ - const: sophgo,sg2042-pcie-msi
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ const: msi
+
+ msi-parent: true
+
+ sophgo,pcie-port:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ SG2042 uses Cadence IP, every IP is composed of 2 cores(called link0
+ & link1 as Cadence's term). "sophgo,pcie-port" is used to identify which
+ core/link the pcie host controller node corresponds to.
+
+ The Cadence IP has two modes of operation, selected by a strap pin.
+
+ In the single-link mode, the Cadence PCIe core instance associated
+ with Link0 is connected to all the lanes and the Cadence PCIe core
+ instance associated with Link1 is inactive.
+
+ In the dual-link mode, the Cadence PCIe core instance associated
+ with Link0 is connected to the lower half of the lanes and the
+ Cadence PCIe core instance associated with Link1 is connected to
+ the upper half of the lanes.
+
+ SG2042 contains 2 Cadence IPs and configures the Cores as below:
+
+ +-- Core(Link0) <---> pcie_rc0 +-----------------+
+ | | |
+ Cadence IP 1 --+ | cdns_pcie0_ctrl |
+ | | |
+ +-- Core(Link1) <---> disabled +-----------------+
+
+ +-- Core(Link0) <---> pcie_rc1 +-----------------+
+ | | |
+ Cadence IP 2 --+ | cdns_pcie1_ctrl |
+ | | |
+ +-- Core(Link1) <---> pcie_rc2 +-----------------+
+
+ pcie_rcX is pcie node ("sophgo,sg2042-pcie-host") defined in DTS.
+ cdns_pcie0_ctrl is syscon node ("sophgo,sg2042-pcie-ctrl") defined in DTS
+
+ cdns_pcieX_ctrl contains some registers shared by pcie_rcX, even two
+ RC(Link)s may share different bits of the same register. For example,
+ cdns_pcie1_ctrl contains registers shared by link0 & link1 for Cadence IP 2.
+
+ "sophgo,pcie-port" is defined to flag which core(link) the rc maps to, with
+ this we can know what registers(bits) we should use.
+
+ sophgo,syscon-pcie-ctrl:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the PCIe System Controller DT node. It's required to
+ access some MSI operation registers shared by PCIe RCs.
+
+allOf:
+ - $ref: cdns-pcie-host.yaml#
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - vendor-id
+ - device-id
+ - sophgo,syscon-pcie-ctrl
+ - sophgo,pcie-port
+
+additionalProperties: true
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ pcie@62000000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x62000000 0x00800000>,
+ <0x48000000 0x00001000>;
+ reg-names = "reg", "cfg";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
+ <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
+ bus-range = <0x80 0xbf>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ sophgo,pcie-port = <0>;
+ sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>;
+ msi-parent = <&msi_pcie>;
+ msi_pcie: msi {
+ compatible = "sophgo,sg2042-pcie-msi";
+ msi-controller;
+ interrupt-parent = <&intc>;
+ interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ };
+ };
--
2.34.1