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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org With the latest spec adding configurable endianness, we thought we should try putting together a proof of concept riscv64 big endian. The full information is documented on our gitlab[1] which includes source repositories, build information and project documentation. We have a minimal buildroot, qemu and kernel working on QEMU. As this is a work in progress any review or help is appreciated. [1] https://gitlab.com/CodethinkLabs/riscv_bigendian _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv