Re: [PATCH] riscv: select DMA_DIRECT_REMAP by RISCV_ISA_SVPBMT and ERRATA_THEAD_MAE

Alexandre Ghiti
2025-02-17T12:30:32Z

Hi Sergey,

On 16/01/2025 18:29, Sergey Matyukevich wrote:
> Select DMA_DIRECT_REMAP for the RISC-V extensions that allow to set
> page-based memory types in PTEs according to the requested DMA
> attributes. This is the purpose of Svpbmt or XTheadMae extensions.
> Zicbom or XTheadCmo serve a different purpose, providing instructions
> to flush/invalidate cache blocks.
>
> Fixes: 381cae169853 ("riscv: only select DMA_DIRECT_REMAP from RISCV_ISA_ZICBOM and ERRATA_THEAD_PBMT")
>
> Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
> ---
> arch/riscv/Kconfig | 2 +-
> arch/riscv/Kconfig.errata | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index d4a7ca0388c0..a5dabb744009 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -603,6 +603,7 @@ config RISCV_ISA_SVPBMT
> depends on 64BIT && MMU
> depends on RISCV_ALTERNATIVE
> default y
> + select DMA_DIRECT_REMAP

From what I read, DMA_DIRECT_MAP relies on the ability to map pages
uncached (pgprot_dmacoherent() here
https://elixir.bootlin.com/linux/v6.13.2/source/kernel/dma/pool.c#L104).
But CONFIG_RISCV_ISA_SVPBMT does not guarantee that the underlying
platform supports svpbmt so to me it is wrong to select DMA_DIRECT_MAP,
we would need some runtime check instead.

> help
> Adds support to dynamically detect the presence of the Svpbmt
> ISA-extension (Supervisor-mode: page-based memory types) and
> @@ -787,7 +788,6 @@ config RISCV_ISA_ZICBOM
> depends on RISCV_ALTERNATIVE
> default y
> select RISCV_DMA_NONCOHERENT

And in the same way, we should not enable RISCV_DMA_NONCOHERENT since
CONFIG_RISCV_ISA_ZICBOM does guarantee the presence of zicbom. Because
then in mm/dma-noncoherent.c, the cache flush operations are nops.

Or am I missing something?

Thanks,

Alex

> - select DMA_DIRECT_REMAP
> help
> Adds support to dynamically detect the presence of the ZICBOM
> extension (Cache Block Management Operations) and enable its
> diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> index 2acc7d876e1f..3bcae5bd3231 100644
> --- a/arch/riscv/Kconfig.errata
> +++ b/arch/riscv/Kconfig.errata
> @@ -86,6 +86,7 @@ config ERRATA_THEAD_MAE
> bool "Apply T-Head's memory attribute extension (XTheadMae) errata"
> depends on ERRATA_THEAD && 64BIT && MMU
> select RISCV_ALTERNATIVE_EARLY
> + select DMA_DIRECT_REMAP
> default y
> help
> This will apply the memory attribute extension errata to handle the
> @@ -96,7 +97,6 @@ config ERRATA_THEAD_MAE
> config ERRATA_THEAD_CMO
> bool "Apply T-Head cache management errata"
> depends on ERRATA_THEAD && MMU
> - select DMA_DIRECT_REMAP
> select RISCV_DMA_NONCOHERENT
> select RISCV_NONSTANDARD_CACHE_OPS
> default y