From: Conor Dooley <conor@kernel.org>
To: Rajnesh Kanwal <rkanwal@rivosinc.com>
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-perf-users@vger.kernel.org, adrian.hunter@intel.com,
alexander.shishkin@linux.intel.com, ajones@ventanamicro.com,
anup@brainfault.org, acme@kernel.org, atishp@rivosinc.com,
beeman@rivosinc.com, brauner@kernel.org, heiko@sntech.de,
irogers@google.com, mingo@redhat.com, james.clark@arm.com,
renyu.zj@linux.alibaba.com, jolsa@kernel.org,
jisheng.teoh@starfivetech.com, palmer@dabbelt.com,
will@kernel.org, kaiwenxue1@gmail.com, vincent.chen@sifive.com
Subject: Re: [PATCH v2 4/7] dt-bindings: riscv: add Sxctr ISA extension description
Date: Mon, 20 Jan 2025 18:49:56 +0000 [thread overview]
Message-ID: <20250120-twisted-reward-b3b620c80368@spud> (raw)
In-Reply-To: <20250116230955.867152-5-rkanwal@rivosinc.com>
[-- Attachment #1.1: Type: text/plain, Size: 2045 bytes --]
On Thu, Jan 16, 2025 at 11:09:52PM +0000, Rajnesh Kanwal wrote:
> Add the S[m|s]ctr ISA extension description.
>
> Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
> ---
> .../devicetree/bindings/riscv/extensions.yaml | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 848354e3048f..8322503f0773 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -167,6 +167,13 @@ properties:
> extension allows other ISA extension to use indirect CSR access
> mechanism in M-mode.
>
> + - const: smctr
> + description: |
> + The standard Smctr supervisor-level extension for the machine mode
> + to enable recording limited branch history in a register-accessible
> + internal core storage. Smctr depend on both the implementation of
> + S-mode and the Sscsrind extension.
Please, like the other extensions, cite the commit (and repo) where the
extension was frozen or ratified.
> +
> - const: sscsrind
> description: |
> The standard Sscsrind supervisor-level extension extends the
> @@ -193,6 +200,13 @@ properties:
> and mode-based filtering as ratified at commit 01d1df0 ("Add ability
> to manually trigger workflow. (#2)") of riscv-count-overflow.
>
> + - const: ssctr
> + description: |
> + The standard Ssctr supervisor-level extension enables recording of
> + limited branch history in a register-accessible internal core
> + storage. Ssctr depend on both the implementation of S-mode and the
> + Sscsrind extension.
> +
> - const: ssnpm
> description: |
> The standard Ssnpm extension for next-mode pointer masking as
> --
> 2.34.1
>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2025-01-20 18:51 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-16 23:09 [PATCH v2 0/7] riscv: pmu: Add support for Control Transfer Records Ext Rajnesh Kanwal
2025-01-16 23:09 ` [PATCH v2 1/7] perf: Increase the maximum number of samples to 256 Rajnesh Kanwal
2025-02-20 18:51 ` Ian Rogers
2025-04-17 12:51 ` Rajnesh Kanwal
2025-05-21 10:47 ` Rajnesh Kanwal
2025-05-21 15:36 ` Ian Rogers
2025-05-21 17:40 ` Rajnesh Kanwal
2025-01-16 23:09 ` [PATCH v2 2/7] riscv: pmu: Add Control transfer records CSR definations Rajnesh Kanwal
2025-01-16 23:09 ` [PATCH v2 3/7] riscv: Add Control Transfer Records extension parsing Rajnesh Kanwal
2025-01-16 23:09 ` [PATCH v2 4/7] dt-bindings: riscv: add Sxctr ISA extension description Rajnesh Kanwal
2025-01-17 7:26 ` Krzysztof Kozlowski
2025-01-20 14:31 ` Rajnesh Kanwal
2025-01-20 18:49 ` Conor Dooley [this message]
2025-01-16 23:09 ` [PATCH v2 5/7] riscv: pmu: Add infrastructure for Control Transfer Record Rajnesh Kanwal
2025-01-16 23:09 ` [PATCH v2 6/7] riscv: pmu: Add driver for Control Transfer Records Ext Rajnesh Kanwal
2025-01-16 23:09 ` [PATCH v2 7/7] riscv: pmu: Integrate CTR Ext support in riscv_pmu_dev driver Rajnesh Kanwal
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250120-twisted-reward-b3b620c80368@spud \
--to=conor@kernel.org \
--cc=acme@kernel.org \
--cc=adrian.hunter@intel.com \
--cc=ajones@ventanamicro.com \
--cc=alexander.shishkin@linux.intel.com \
--cc=anup@brainfault.org \
--cc=atishp@rivosinc.com \
--cc=beeman@rivosinc.com \
--cc=brauner@kernel.org \
--cc=heiko@sntech.de \
--cc=irogers@google.com \
--cc=james.clark@arm.com \
--cc=jisheng.teoh@starfivetech.com \
--cc=jolsa@kernel.org \
--cc=kaiwenxue1@gmail.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=mingo@redhat.com \
--cc=palmer@dabbelt.com \
--cc=renyu.zj@linux.alibaba.com \
--cc=rkanwal@rivosinc.com \
--cc=vincent.chen@sifive.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox