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Thu, 30 Jan 2025 00:50:21 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::76fd]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c0ec7e6sm1332565f8f.19.2025.01.30.00.50.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2025 00:50:21 -0800 (PST) Date: Thu, 30 Jan 2025 09:50:20 +0100 From: Andrew Jones To: Chin Yik Ming Cc: conor@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, charlie@rivosinc.com, samuel.holland@sifive.com, cleger@rivosinc.com, andybnac@gmail.com, alexghiti@rivosinc.com, peterlin@andestech.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] riscv: Simplify base extension checks and direct boolean return Message-ID: <20250130-77bf6cf799f468b43fb5382e@orel> References: <20250129203843.1136838-1-yikming2222@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250129203843.1136838-1-yikming2222@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250130_005023_569431_ADF59FF3 X-CRM114-Status: GOOD ( 17.41 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Jan 30, 2025 at 04:38:43AM +0800, Chin Yik Ming wrote: > Reduce three lines checking to single line using a ternary conditional > expression for getting the base extension word. In addition, the > test_bit macro function already return a boolean which matches the > return type of the caller, so directly return the result of the test_bit > macro function. > > Signed-off-by: Chin Yik Ming > --- > arch/riscv/kernel/cpufeature.c | 6 ++---- > arch/riscv/kernel/vendor_extensions.c | 2 +- > 2 files changed, 3 insertions(+), 5 deletions(-) > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index c0916ed318c2..32525b69ab99 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -49,9 +49,7 @@ struct riscv_isainfo hart_isa[NR_CPUS]; > */ > unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap) > { > - if (!isa_bitmap) > - return riscv_isa[0]; > - return isa_bitmap[0]; > + return !isa_bitmap ? riscv_isa[0] : isa_bitmap[0]; > } > EXPORT_SYMBOL_GPL(riscv_isa_extension_base); > > @@ -72,7 +70,7 @@ bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned i > if (bit >= RISCV_ISA_EXT_MAX) > return false; > > - return test_bit(bit, bmap) ? true : false; > + return test_bit(bit, bmap); > } > EXPORT_SYMBOL_GPL(__riscv_isa_extension_available); > > diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vendor_extensions.c > index a8126d118341..62f55bc779e9 100644 > --- a/arch/riscv/kernel/vendor_extensions.c > +++ b/arch/riscv/kernel/vendor_extensions.c > @@ -51,6 +51,6 @@ bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsig > if (bit >= RISCV_ISA_VENDOR_EXT_MAX) > return false; > > - return test_bit(bit, bmap->isa) ? true : false; > + return test_bit(bit, bmap->isa); > } > EXPORT_SYMBOL_GPL(__riscv_isa_vendor_extension_available); > -- > 2.34.1 > Since the changes are harmless and I do prefer the way the code looks with them, Reviewed-by: Andrew Jones but these types of changes are pretty much just pointless churn... Thanks, drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv