Re: [PATCH v4 3/3] riscv: dts: canaan: Add clock initial support for K230

Xukai Wang
2025-02-18T17:37:28Z

On 2025/2/19 01:00, Conor Dooley wrote:
> On Mon, Feb 17, 2025 at 10:45:18PM +0800, Xukai Wang wrote:
>> + sysclk: clock-controller@91102000 {
>> + compatible = "canaan,k230-clk";
>> + reg = <0x0 0x91102000 0x0 0x1000>,
>> + <0x0 0x91100000 0x0 0x1000>;
>> + clocks = <&osc24m>;
>> + clock-output-names = "CPU0_ACLK", "CPU0_PLIC", "CPU0_NOC_DDRCP4",
>> + "CPU0_PCLK", "PMU_PCLK", "HS_HCLK_HIGH_SRC",
>> + "HS_HCLK_HIGH_GATE", "HS_HCLK_SRC",
>> + "HS_SD0_HS_AHB_GAT", "HS_SD1_HS_AHB_GAT",
>> + "HS_SSI1_HS_AHB_GA", "HS_SSI2_HS_AHB_GA",
>> + "HS_USB0_HS_AHB_GA", "HS_USB1_HS_AHB_GA",
>> + "HS_SSI0_AXI", "HS_SSI1", "HS_SSI2",
>> + "HS_QSPI_AXI_SRC", "HS_SSI1_ACLK_GATE",
>> + "HS_SSI2_ACLK_GATE", "HS_SD_CARD_SRC",
>> + "HS_SD0_CARD_TX", "HS_SD1_CARD_TX",
>> + "HS_SD_AXI_SRC", "HS_SD0_AXI_GATE",
>> + "HS_SD1_AXI_GATE", "HS_SD0_BASE_GATE",
>> + "HS_SD1_BASE_GATE", "HS_OSPI_SRC",
>> + "HS_USB_REF_51M", "HS_SD_TIMER_SRC",
>> + "HS_SD0_TIMER_GATE", "HS_SD1_TIMER_GATE",
>> + "HS_USB0_REFERENCE", "HS_USB1_REFERENCE";
>> + #clock-cells = <1>;
>> + };
> Apologies for not commenting on it until now, but this patch seems like
> there's some hunks missing from it. I'd expect you to remove the dummy
> "apb-clk-clock" from the dts and replace it with a real one sourced from
> the newly added clock controller.

Thanks for your time.

I've modified all nodes that previously depended on apb_clk， and they
are now referencing the new clock controller.