Re: [PATCH v4 1/3] dt-bindings: clock: Add bindings for Canaan K230 clock controller

Stephen Boyd
2025-02-18T22:01:50Z

Quoting Xukai Wang (2025-02-17 06:45:16)
> diff --git a/Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml b/Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..d7220fa30e4699a68fa5279c04abc63c1905fa4a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml
> @@ -0,0 +1,43 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/canaan,k230-clk.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Canaan Kendryte K230 Clock
> +
> +maintainers:
> + - Xukai Wang <kingxukai@zohomail.com>

Is this missing a description of the device?

> +
> +properties:
> + compatible:
> + const: canaan,k230-clk
> +
> + reg:
> + items:
> + - description: PLL control registers.
> + - description: Sysclk control registers.
> +
> + clocks:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clock-controller@91102000 {
> + compatible = "canaan,k230-clk";
> + reg = <0x91102000 0x1000>,

Is there a reason why the PLL range comes first? What's at 0x91101000?
More clk hardware?

> + <0x91100000 0x1000>;
> + clocks = <&osc24m>;
> + #clock-cells = <1>;
> + };