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Mon, 03 Mar 2025 23:13:17 -0800 (PST) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with UTF8SMTPSA id d75a77b69052e-474691a1f2csm69783811cf.13.2025.03.03.23.13.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Mar 2025 23:13:17 -0800 (PST) From: Inochi Amaoto To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Johan Hovold , Shashank Babu Chinta Venkata , Niklas Cassel Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Yixun Lan , Longbin Li Subject: [PATCH 0/2] riscv: sophgo Add PCIe support to Sophgo SG2044 SoC Date: Tue, 4 Mar 2025 15:12:36 +0800 Message-ID: <20250304071239.352486-1-inochiama@gmail.com> X-Mailer: git-send-email 2.48.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250303_231318_780852_93D6833B X-CRM114-Status: GOOD ( 11.05 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Sophgo's SG2044 SoC uses Synopsys Designware PCIe core to implement RC mode. For legacy interrupt, the PCIe controller on SG2044 implement its own legacy interrupt controller. For MSI/MSI-X, it use an external interrupt controller to handle. The external MSI interrupt controller patch can be found on [1]. As SG2044 needs a mirror change to support the way to send MSI message and different irq number. [1] https://lore.kernel.org/all/20250303111648.1337543-1-inochiama@gmail.com Changed from v1: - https://lore.kernel.org/all/20250221013758.370936-1-inochiama@gmail.comq 1. patch 1: remove dma-coherent property 2. patch 2: remove unused reset 3. patch 2: fix Kconfig menu title and reorder the entry 4. patch 2: use FIELD_GET/FIELD_PREP to simplify the code. 5. patch 2: rename the irq handle function to match the irq_chip name Inochi Amaoto (2): dt-bindings: pci: Add Sophgo SG2044 PCIe host PCI: sophgo-dwc: Add Sophgo SG2044 PCIe driver .../bindings/pci/sophgo,sg2044-pcie.yaml | 122 ++++++++ drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-dw-sophgo.c | 270 ++++++++++++++++++ 4 files changed, 403 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml create mode 100644 drivers/pci/controller/dwc/pcie-dw-sophgo.c -- 2.48.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv