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[31.30.173.28]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d43f32fb3sm106377745e9.2.2025.03.22.05.11.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Mar 2025 05:11:29 -0700 (PDT) Date: Sat, 22 Mar 2025 13:11:28 +0100 From: Andrew Jones To: =?utf-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= Cc: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Samuel Holland Subject: Re: [PATCH v4 03/18] riscv: sbi: add FWFT extension interface Message-ID: <20250322-a87faa18fe5b54b7cb61b353@orel> References: <20250317170625.1142870-1-cleger@rivosinc.com> <20250317170625.1142870-4-cleger@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250317170625.1142870-4-cleger@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250322_051132_216545_1D3C2F88 X-CRM114-Status: GOOD ( 22.09 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Mar 17, 2025 at 06:06:09PM +0100, Cl=E9ment L=E9ger wrote: > This SBI extensions enables supervisor mode to control feature that are > under M-mode control (For instance, Svadu menvcfg ADUE bit, Ssdbltrp > DTE, etc). Add an interface to set local features for a specific cpu > mask as well as for the online cpu mask. > = > Signed-off-by: Cl=E9ment L=E9ger > --- > arch/riscv/include/asm/sbi.h | 20 +++++++++++ > arch/riscv/kernel/sbi.c | 69 ++++++++++++++++++++++++++++++++++++ > 2 files changed, 89 insertions(+) > = > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h > index d11d22717b49..1cecfa82c2e5 100644 > --- a/arch/riscv/include/asm/sbi.h > +++ b/arch/riscv/include/asm/sbi.h > @@ -503,6 +503,26 @@ int sbi_remote_hfence_vvma_asid(const struct cpumask= *cpu_mask, > unsigned long asid); > long sbi_probe_extension(int ext); > = > +int sbi_fwft_local_set_cpumask(const cpumask_t *mask, u32 feature, > + unsigned long value, unsigned long flags); > +/** > + * sbi_fwft_local_set() - Set a feature on all online cpus > + * @feature: The feature to be set > + * @value: The feature value to be set > + * @flags: FWFT feature set flags > + * > + * Return: 0 on success, appropriate linux error code otherwise. > + */ > + static inline int sbi_fwft_local_set(u32 feature, unsigned long value, > + unsigned long flags) > + { > + return sbi_fwft_local_set_cpumask(cpu_online_mask, feature, value, > + flags); Let flags stick out. We have 100 chars. > + } > + > +int sbi_fwft_get(u32 feature, unsigned long *value); > +int sbi_fwft_set(u32 feature, unsigned long value, unsigned long flags); > + > /* Check if current SBI specification version is 0.1 or not */ > static inline int sbi_spec_is_0_1(void) > { > diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c > index 1989b8cade1b..d41a5642be24 100644 > --- a/arch/riscv/kernel/sbi.c > +++ b/arch/riscv/kernel/sbi.c > @@ -299,6 +299,75 @@ static int __sbi_rfence_v02(int fid, const struct cp= umask *cpu_mask, > return 0; > } > = > +/** > + * sbi_fwft_get() - Get a feature for the local hart > + * @feature: The feature ID to be set > + * @value: Will contain the feature value on success > + * > + * Return: 0 on success, appropriate linux error code otherwise. > + */ > +int sbi_fwft_get(u32 feature, unsigned long *value) > +{ > + return -EOPNOTSUPP; > +} > + > +/** > + * sbi_fwft_set() - Set a feature on the local hart > + * @feature: The feature ID to be set > + * @value: The feature value to be set > + * @flags: FWFT feature set flags > + * > + * Return: 0 on success, appropriate linux error code otherwise. > + */ > +int sbi_fwft_set(u32 feature, unsigned long value, unsigned long flags) > +{ > + return -EOPNOTSUPP; > +} > + > +struct fwft_set_req { > + u32 feature; > + unsigned long value; > + unsigned long flags; > + atomic_t error; > +}; > + > +static void cpu_sbi_fwft_set(void *arg) > +{ > + struct fwft_set_req *req =3D arg; > + int ret; > + > + ret =3D sbi_fwft_set(req->feature, req->value, req->flags); > + if (ret) > + atomic_set(&req->error, ret); > +} > + > +/** > + * sbi_fwft_local_set() - Set a feature for the specified cpumask sbi_fwft_local_set_cpumask > + * @mask: CPU mask of cpus that need the feature to be set > + * @feature: The feature ID to be set > + * @value: The feature value to be set > + * @flags: FWFT feature set flags > + * > + * Return: 0 on success, appropriate linux error code otherwise. > + */ > +int sbi_fwft_local_set_cpumask(const cpumask_t *mask, u32 feature, > + unsigned long value, unsigned long flags) > +{ > + struct fwft_set_req req =3D { > + .feature =3D feature, > + .value =3D value, > + .flags =3D flags, > + .error =3D ATOMIC_INIT(0), > + }; > + > + if (feature & SBI_FWFT_GLOBAL_FEATURE_BIT) > + return -EINVAL; > + > + on_each_cpu_mask(mask, cpu_sbi_fwft_set, &req, 1); > + > + return atomic_read(&req.error); > +} > + > /** > * sbi_set_timer() - Program the timer for next timer event. > * @stime_value: The value after which next timer event should fire. > -- = > 2.47.2 > Otherwise, Reviewed-by: Andrew Jones _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv